| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Rename ExpandISelPseudo->FinalizeISel, delay register reservation | Matt Arsenault | 2019-06-19 | 1 | -1/+1 |
| | | | | | | | | | | | | This allows targets to make more decisions about reserved registers after isel. For example, now it should be certain there are calls or stack objects in the frame or not, which could have been introduced by legalization. Patch by Matthias Braun llvm-svn: 363757 | ||||
| * | Fix an incorrectly configured test. | Jeremy Morse | 2019-01-29 | 1 | -0/+2 |
| | | | | | | | This should have had a target triple in it, my mistake. llvm-svn: 352460 | ||||
| * | [DebugInfo][DAG] Avoid re-ordering of DBG_VALUEs | Jeremy Morse | 2019-01-28 | 1 | -0/+46 |
| This patch improves the placement of DBG_VALUEs when by SelectionDAG, which as documented in PR40427 can go very wrong. At the core of this is ProcessSourceNode, which assumes the last instruction in a BB is the start of the last processed IR instruction, which isn't always true. Instead, use a helper function to call InstrEmitter::EmitNode, that records before-and-after iterators and determines the first of any new instruction created during emission. This is passed to ProcessSourceNode, which can then make more elightened decisions about ordering for DBG_VALUE placement. Differential revision: https://reviews.llvm.org/D57163 llvm-svn: 352350 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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