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* [SystemZ] Make the CCRegs regclass non-allocatable.Jonas Paulsson2015-10-292-1/+35
| | | | | | | | | | | | | | | | | | | | | This was discovered to be necessary while running memchr-01.ll with -verify-machinstrs, because it is not allowed to have a phys reg live accross block boundaries while on SSA form, if the register is allocatable (expect in entry block and landing pads). In this test case, stringRRE pseudos are expanded after isel by adding a loop block which produces a live out CC register. To make the test pass, it was also necessary to not say that StringRRELoop pseudo uses R0L, this is only true for the StringRRE opcode. -verify-machineinstrs added to memchr-01.ll test. New test case int-cmp-51.ll to test that MachineCSE can eliminate an identical compare (which it couldn't do before). Reviewed by Ulrich Weigand llvm-svn: 251634
* AMDGPU/SI: handle undef for llvm.SI.packf16Marek Olsak2015-10-291-0/+29
| | | | llvm-svn: 251632
* AMDGPU/SI: use S_OR for fneg (fabs f32)Marek Olsak2015-10-291-18/+9
| | | | llvm-svn: 251631
* AMDGPU/SI: use S_AND for i1 truncMarek Olsak2015-10-291-4/+4
| | | | llvm-svn: 251630
* [mips] wrong opcode for ll/sc instructions on mipsr6 when -integrated-as is usedZoran Jovanovic2015-10-291-0/+32
| | | | | | | | | | | | | | | Summary: This commit resolves wrong opcodes for ll and sc instructions for r6 architecutres, which were generated in method MipsTargetLowering::emitAtomicBinary. Author: Jelena.Losic Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D13593 llvm-svn: 251629
* [mips] Check the register class before replacing materializations of zero ↵Vasileios Kalintiris2015-10-291-0/+8
| | | | | | | | | | | | | | | | | | | | | | with $zero in microMIPS. Summary: The microMIPS register class GPRMM16 does not contain the $zero register. However, MipsSEDAGToDAGISel::replaceUsesWithZeroReg() would replace uses of the $dst register: [d]addiu, $dst, $zero, 0 with the $zero register, without checking for membership in the register class of the target machine operand. Reviewers: dsanders Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13984 llvm-svn: 251622
* [MachineVerifier] Analyze MachineMemOperands for mem-to-mem moves.Jonas Paulsson2015-10-291-1/+1
| | | | | | | | | | | | | Since the verifier will give false reports if it incorrectly thinks MI is loading or storing using an FI, it is necessary to scan memoperands and find out how the FI is used in the instruction. This should be relatively rare. Needed to make CodeGen/SystemZ/spill-01.ll pass, which now runs with this flag. Reviewed by Quentin Colombet. llvm-svn: 251620
* [WebAssembly] Update opcode name format for conversionsJF Bastien2015-10-291-21/+21
| | | | | | | | | | | | Summary: Conversion opcode name format should be f64.convert_u/i64 not f64_convert_u Author: s3ththompson Reviewers: jfb Subscribers: sunfish, jfb, llvm-commits, dschuff Differential Revision: http://reviews.llvm.org/D14160 llvm-svn: 251613
* [PowerPC] Recurse through constants when looking for TLS globalsHal Finkel2015-10-281-0/+40
| | | | | | | | | | | | | We cannot form ctr-based loops around function calls, including calls to __tls_get_addr used for PIC TLS variables. References to such TLS variables, however, might be buried within constant expressions, and so we need to search the entire constant expression to be sure that no references to such TLS variables exist. Fixes PR25256, reported by Eric Schweitz. This is a slightly-modified version of the patch suggested by Eric in the bug report, and a test case I created. llvm-svn: 251582
* [PowerPC] Don't return unsupported register classes for asm constraintsHal Finkel2015-10-281-0/+14
| | | | | | | | | As a follow-up to r251566, do the same for the other optionally-supported register classes (mostly for vector registers). Don't return an unavailable register class (which would cause an assert later), but fail cleanly when provided an unsupported inline asm constraint. llvm-svn: 251575
* ARM: add support for WatchOS's compact unwind information.Tim Northover2015-10-284-3/+67
| | | | llvm-svn: 251573
* ARM: teach backend about WatchOS and TvOS libcalls.Tim Northover2015-10-282-0/+170
| | | | | | | The most substantial changes are again for watchOS: libcalls are hard-float if needed and sincos has a different calling convention. llvm-svn: 251571
* ARM: add backend support for the ABI used in WatchOSTim Northover2015-10-281-0/+146
| | | | | | | At the LLVM level this ABI is essentially a minimal modification of AAPCS to support 16-byte alignment for vector types and the stack. llvm-svn: 251570
* [PowerPC] Cleanly reject asm crbit constraint with -crbitsHal Finkel2015-10-281-0/+16
| | | | | | | When crbits are disabled, cleanly reject the constraint (return the register class only to cause an assert later). llvm-svn: 251566
* [PowerPC] Fix CodeGen/PowerPC/crbit-asm.ll test for -O1Hal Finkel2015-10-281-1/+2
| | | | | | | | | Add the crbits processor feature so that the test can be run at -O1, etc. regardless of the default crbits setting. Fixes PR23778. llvm-svn: 251548
* WebAssembly: disable some loop-idiom recognitionJF Bastien2015-10-281-0/+53
| | | | | | | memset/memcpy aren't fully supported yet. We should invert this test once they are supported. llvm-svn: 251534
* [PowerPC] Replace cntlz[.] with cntlzw[.]Hal Finkel2015-10-283-3/+3
| | | | | | | | | | | | | | | | | | | cntlz is the old POWER mnemonic. cntlzw is the PowerPC mnemonic. This change fixes an issue when -no-integrated-as: The opcode cntlz is unrecognized by gas Alias the POWER mnemonic cntlz[.] to the PowerPC mnemonic cntlzw[.] This is done for because the POWER cntlz mnemonic has be used by LLVM for a very long time. We need to make sure that assembly programs that are using the cntlz[.] do not break with this change. Change PowerPC tests to reflect the insn change from cntlz to cntlzw. Add assembly test to verify cntlz[.] is encoded correctly. Patch by Tom Rix! llvm-svn: 251489
* [SelectionDAG] Don't inspect !range metadata for extended loadsSanjoy Das2015-10-281-0/+12
| | | | | | | | | | | | | | | | | | Summary: Don't call `computeKnownBitsFromRangeMetadata` for extended loads -- this can cause a mismatch between the width of the !range metadata and the width of the APInt's accumulating `KnownZero` (and `KnownOne` in the future). This isn't a problem now, but will be after a future change. Note: this can be made more aggressive in the future. Reviewers: nlewycky Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14107 llvm-svn: 251486
* [X86][AVX512] Test UNPCK with non-sequential scalarsSimon Pilgrim2015-10-272-4/+112
| | | | | | Missing tests for r251297 llvm-svn: 251453
* Use the 'arcp' fast-math-flag when combining repeated FP divisorsSanjay Patel2015-10-271-10/+59
| | | | | | | | | | | | This is a usage of the IR-level fast-math-flags now that they are propagated to SDNodes. This was originally part of D8900. Removing the global 'enable-unsafe-fp-math' checks will require auto-upgrade and possibly other changes. Differential Revision: http://reviews.llvm.org/D9708 llvm-svn: 251450
* [AArch64]Merge halfword loads into a 32-bit loadJun Bum Lim2015-10-271-0/+49
| | | | | | | | | | | | | | | | This recommits r250719, which caused a failure in SPEC2000.gcc because of the incorrect insert point for the new wider load. Convert two halfword loads into a single 32-bit word load with bitfield extract instructions. For example : ldrh w0, [x2] ldrh w1, [x2, #2] becomes ldr w0, [x2] ubfx w1, w0, #16, #16 and w0, w0, #ffff llvm-svn: 251438
* Create a new interface addSuccessorWithoutWeight(MBB*) in MBB to add ↵Cong Hou2015-10-272-4/+4
| | | | | | | | | | | | | | successors when optimization is disabled. When optimization is disabled, edge weights that are stored in MBB won't be used so that we don't have to store them. Currently, this is done by adding successors with default weight 0, and if all successors have default weights, the weight list will be empty. But that the weight list is empty doesn't mean disabled optimization (as is stated several times in MachineBasicBlock.cpp): it may also mean all successors just have default weights. We should discourage using default weights when adding successors, because it is very easy for users to forget update the correct edge weights instead of using default ones (one exception is that the MBB only has one successor). In order to detect such usages, it is better to differentiate using default weights from the case when optimizations is disabled. In this patch, a new interface addSuccessorWithoutWeight(MBB*) is created for when optimization is disabled. In this case, MBB will try to maintain an empty weight list, but it cannot guarantee this as for many uses of addSuccessor() whether optimization is disabled or not is not checked. But it can guarantee that if optimization is enabled, then the weight list always has the same size of the successor list. Differential revision: http://reviews.llvm.org/D13963 llvm-svn: 251429
* [X86][AVX512] [X86][AVX512] add convert float to halfAsaf Badouh2015-10-271-0/+19
| | | | | | | | convert float to half with mask/maskz for the reg to reg version and mask for the reg to mem version (there is no maskz version for reg to mem). Differential Revision: http://reviews.llvm.org/D14113 llvm-svn: 251409
* [ARM] Expand ROTL and ROTR of vector value typesCharlie Turner2015-10-272-0/+28
| | | | | | | | | | | | Summary: After D13851 landed, we saw backend crashes when compiling the reduced test case included in this patch. The right fix seems to be to allow these vector types for expansion in instruction selection. Reviewers: rengolin, t.p.northover Subscribers: RKSimon, t.p.northover, aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D14082 llvm-svn: 251401
* [X86] Make elfiamcu an OS, not an environment.Michael Kuperstein2015-10-271-1/+1
| | | | | | | | | | GNU tools require elfiamcu to take up the entire OS field, so, e.g. i?86-*-linux-elfiamcu is not considered a legal triple. Make us compatible. Differential Revision: http://reviews.llvm.org/D14081 llvm-svn: 251390
* [x86] replace integer logic ops with packed SSE FP logic opsSanjay Patel2015-10-271-18/+12
| | | | | | | | | | | | | | | | | | | If we have an operand to a bitwise logic op that's already in an XMM register and the result is going to be sent to an XMM register, then use an SSE logic op to avoid moves between the integer and vector register files. Related commits: http://reviews.llvm.org/rL248395 http://reviews.llvm.org/rL248399 http://reviews.llvm.org/rL248404 http://reviews.llvm.org/rL248409 http://reviews.llvm.org/rL248415 This should solve PR22428: https://llvm.org/bugs/show_bug.cgi?id=22428 llvm-svn: 251378
* Fix llc crash processing S/UREM for -Oz builds caused by rL250825.Steve King2015-10-271-0/+257
| | | | | | | | | | | | | | When taking the remainder of a value divided by a constant, visitREM() attempts to convert the REM to a longer but faster sequence of instructions. This conversion calls combine() on a speculative DIV instruction. Commit rL250825 may cause this combine() to return a DIVREM, corrupting nearby nodes. Flow eventually hits unreachable(). This patch adds a test case and a check to prevent visitREM() from trying to convert the REM instruction in cases where a DIVREM is possible. See http://reviews.llvm.org/D14035 llvm-svn: 251373
* add FP logic test cases to show current codegen (PR22428)Sanjay Patel2015-10-261-0/+60
| | | | llvm-svn: 251370
* [x86] Make the vselect-minmax test 2x to 3x faster by deleting all theChandler Carruth2015-10-261-4032/+960
| | | | | | | instructions that aren't relevant for instruction selection of vector min and max. llvm-svn: 251366
* ARM: make sure VFP loads and stores are properly aligned.Tim Northover2015-10-261-0/+98
| | | | | | | Both VLDRS and VLDRD fault if the memory is not 4 byte aligned, which wasn't really being checked before, leading to faults at runtime. llvm-svn: 251352
* Fix tests.Peter Collingbourne2015-10-261-1/+1
| | | | llvm-svn: 251343
* ARM/ELF: Better codegen for global variable addresses.Peter Collingbourne2015-10-264-66/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In PIC mode we were previously computing global variable addresses (or GOT entry addresses) by adding the PC, the PC-relative GOT displacement and the GOT-relative symbol/GOT entry displacement. Because the latter two displacements are fixed, we ended up performing one more addition than necessary. This change causes us to compute addresses using a single PC-relative displacement, resulting in a shorter code sequence. This reduces code size by about 4% in a recent build of Chromium for Android. As a result of this change we no longer need to compute the GOT base address in the ARM backend, which allows us to remove the Global Base Reg pass and SDAG lowering for the GOT. We also now no longer use the GOT when addressing a symbol which is known to be defined in the same linkage unit. Specifically, the symbol must have either hidden visibility or a strong definition in the current module in order to not use the the GOT. This is a change from the previous behaviour where we would use the GOT to address externally visible symbols defined in the same module. I think the only cases where this could matter are cases involving symbol interposition, but we don't really support that well anyway. Differential Revision: http://reviews.llvm.org/D13650 llvm-svn: 251322
* [SystemZ] LTGFR use regclass should be GR32, not GR64.Jonas Paulsson2015-10-261-1/+2
| | | | | | | Discovered by testing int-cmp-44.ll with -verify-machineinstrs (added to test run). llvm-svn: 251299
* [SystemZ] Also clear kill flag for index reg in splitMove().Jonas Paulsson2015-10-261-1/+1
| | | | | | | Discovered by running fp-move-05.ll with -verify-machineinstrs (added to test case run). llvm-svn: 251298
* [SystemZ] Don't forget the CC def op on LTEBRCompare pseudosJonas Paulsson2015-10-261-1/+1
| | | | | | | Discovered by running fp-cmp-02.ll with -verify-machineinstrs (now added to test run). llvm-svn: 251297
* [SystemZ] Tie operands in SystemZShorteInst if MI becomes 2-address.Jonas Paulsson2015-10-261-1/+1
| | | | | | | | Discovered by testing fp-add-02.ll with -verify-machineinstrs. Test case updated to always run with -verify-machineinstrs. llvm-svn: 251296
* [mips] Check for the correct error message in tests for interrupt attributes.Vasileios Kalintiris2015-10-266-33/+27
| | | | | | | | Instead of XFAIL-ing the tests with the wrong usage of the "interrupt" attribute, we should check that we emit the correct error messages to the user. llvm-svn: 251295
* fix test errors (on windows) for commit r251287Igor Breger2015-10-261-2/+2
| | | | llvm-svn: 251288
* AVX512: Enabled VPBROADCASTB lowering for v64i8 vectors.Igor Breger2015-10-261-96/+165
| | | | | | Differential Revision: http://reviews.llvm.org/D13896 llvm-svn: 251287
* [mips] Interrupt attribute support for mips32r2+.Vasileios Kalintiris2015-10-264-0/+277
| | | | | | | | | | | | | | | | | | | Summary: This patch adds support for using the "interrupt" attribute on Mips for interrupt handling functions. At this time only mips32r2+ with the o32 ABI with the static relocation model is supported. Unsupported configurations will be rejected Patch by Simon Dardis (+ clang-format & some trivial changes to follow the LLVM coding standards by me). Reviewers: mpf, dsanders Subscribers: dsanders, vkalintiris, llvm-commits Differential Revision: http://reviews.llvm.org/D10768 llvm-svn: 251286
* AVX-512: Use correct extract vector length.Igor Breger2015-10-261-0/+11
| | | | | | | | Bug https://llvm.org/bugs/show_bug.cgi?id=25318 Differential Revision: http://reviews.llvm.org/D14062 llvm-svn: 251285
* [ARM] Handle the inline asm constraint type 'o'James Molloy2015-10-261-0/+11
| | | | | | This means "memory with offset" and requires very little plumbing to get working. This fixes PR25317. llvm-svn: 251280
* AVX512: Add AVX-512 not materializable instructions. Igor Breger2015-10-261-0/+34
| | | | | | | | | | Otherwise value can be reused , despite its value could be changed - produces incorrect assembler. https://llvm.org/bugs/show_bug.cgi?id=25270 Differential Revision: http://reviews.llvm.org/D14057 llvm-svn: 251275
* [X86][AVX] Regenerate tests.Simon Pilgrim2015-10-251-10/+10
| | | | llvm-svn: 251263
* [X86][SSE4A] Fix for EXTRQI shuffle lowering.Simon Pilgrim2015-10-251-0/+23
| | | | | | Incorrect range test - found during fuzz testing. llvm-svn: 251245
* [X86][SSE] Refreshed tests (missing AVX512 patterns)Simon Pilgrim2015-10-251-0/+270
| | | | llvm-svn: 251238
* Scalarizer for masked.gather and masked.scatter intrinsics.Elena Demikhovsky2015-10-251-0/+85
| | | | | | | | | | When the target does not support these intrinsics they should be converted to a chain of scalar load or store operations. If the mask is not constant, the scalarizer will build a chain of conditional basic blocks. I added isLegalMaskedGather() isLegalMaskedScatter() APIs. Differential Revision: http://reviews.llvm.org/D13722 llvm-svn: 251237
* [X86][SSE] Added tests for shuffling through bitcasts.Simon Pilgrim2015-10-252-3/+103
| | | | llvm-svn: 251236
* [X86][SSE] vector sext/zext tests - remove unnecessary mcpu argumentsSimon Pilgrim2015-10-252-11/+11
| | | | llvm-svn: 251233
* [X86][SSE] shift/rotate tests - remove unnecessary mcpu arguments and ↵Simon Pilgrim2015-10-258-194/+194
| | | | | | regenerate/cleanup llvm-svn: 251232
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