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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2015-10-25 17:40:54 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2015-10-25 17:40:54 +0000 |
| commit | ec6db262e0e115db393cfc046fed8c9fa4b017c0 (patch) | |
| tree | 9b86c75f4dddd9aaf7764585d72e381b80ab8548 /llvm/test/CodeGen | |
| parent | 9c5c7a6ab45c0f56910347ce52759f4350ce3ab2 (diff) | |
| download | bcm5719-llvm-ec6db262e0e115db393cfc046fed8c9fa4b017c0.tar.gz bcm5719-llvm-ec6db262e0e115db393cfc046fed8c9fa4b017c0.zip | |
[X86][SSE4A] Fix for EXTRQI shuffle lowering.
Incorrect range test - found during fuzz testing.
llvm-svn: 251245
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-shuffle-sse4a.ll | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-sse4a.ll b/llvm/test/CodeGen/X86/vector-shuffle-sse4a.ll index 58807b9c0fd..2dd43e2852a 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-sse4a.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-sse4a.ll @@ -296,5 +296,28 @@ define <8 x i16> @shuf_089uuuuu(<8 x i16> %a0, <8 x i16> %a1) { ret <8 x i16> %s } +; +; Special Cases +; + +; Out of range. +define <16 x i8> @shuffle_8_18_uuuuuuuuuuuuuu(<16 x i8> %a, <16 x i8> %b) { +; BTVER1-LABEL: shuffle_8_18_uuuuuuuuuuuuuu: +; BTVER1: # BB#0: +; BTVER1-NEXT: psrld $16, %xmm1 +; BTVER1-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; BTVER1-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] +; BTVER1-NEXT: retq +; +; BTVER2-LABEL: shuffle_8_18_uuuuuuuuuuuuuu: +; BTVER2: # BB#0: +; BTVER2-NEXT: vpsrld $16, %xmm1, %xmm1 +; BTVER2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; BTVER2-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] +; BTVER2-NEXT: retq + %1 = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 18, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> + ret <16 x i8> %1 +} + declare <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64>, i8, i8) nounwind declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8) nounwind |
