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* Prioritize smaller register classes for urgent evictions.Jakob Stoklund Olesen2012-05-301-0/+9
| | | | | | | | | | | | | | It helps compile exotic inline asm. In the test case, normal GR32 virtual registers use up eax-edx so the final GR32_ABCD live range has no registers left. Since all the live ranges were tiny, we had no way of prioritizing the smaller register class. This patch allows tiny unspillable live ranges to be evicted by tiny unspillable live ranges from a smaller register class. <rdar://problem/11542429> llvm-svn: 157715
* Add support for the mips inline asm 'm' output modifier.Eric Christopher2012-05-301-0/+6
| | | | | | Patch by Jack Carter. llvm-svn: 157709
* Switch the canonical FMA term operand order to match both the comment I ↵Owen Anderson2012-05-301-1/+1
| | | | | | wrote and the usual LLVM convention. llvm-svn: 157708
* Teach DAGCombine to canonicalize the position of a constant in the term ↵Owen Anderson2012-05-301-0/+9
| | | | | | operands of an FMA node. llvm-svn: 157707
* it's pointed out that R11 can be used for magic things, and doing things ↵Chris Lattner2012-05-302-17/+16
| | | | | | just for 64-bit registers is silly. Just optimize 3 more. llvm-svn: 157699
* Extend the (abi-irrelevant) return convention to be able to return more than ↵Chris Lattner2012-05-301-0/+17
| | | | | | | | | | | | two values in integer registers. This is already supported by the fastcc convention, but it doesn't hurt to support it in the standard conventions as well. In cases where we can cheat at the calling convention, this allows us to avoid returning things through memory in more cases. llvm-svn: 157698
* [arm-fast-isel] Add support for the llvm.frameaddress() intrinsic.Chad Rosier2012-05-301-0/+100
| | | | | | Patch by Jush Lu <jush.msn@gmail.com>. llvm-svn: 157696
* Teach taildup to update livein set. rdar://11538365Evan Cheng2012-05-301-0/+140
| | | | llvm-svn: 157663
* Add an insertPass API to TargetPassConfig. <rdar://problem/11498613>Bob Wilson2012-05-301-0/+14
| | | | | | | | | | Besides adding the new insertPass function, this patch uses it to enhance the existing -print-machineinstrs so that the MachineInstrs after a specific pass can be printed. Patch by Bin Zeng! llvm-svn: 157655
* Add intrinsics, code gen, assembler and disassembler support for the SSE4a ↵Benjamin Kramer2012-05-291-2/+39
| | | | | | | | | | | extrq and insertq instructions. This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. llvm-svn: 157634
* Add llvm.fabs intrinsic.Peter Collingbourne2012-05-281-0/+21
| | | | llvm-svn: 157594
* These tests used intrinsics with the wrong prototype. They weren't caught ↵Chris Lattner2012-05-273-24/+26
| | | | | | | | | because the old verifier just checked that something "was a pointer", but not that the pointee was correct. llvm-svn: 157544
* SelectionDAGBuilder: When emitting small compare chains for switches order ↵Benjamin Kramer2012-05-261-0/+37
| | | | | | | | | | | | | | them by using edge weights. SimplifyCFG tends to form a lot of 2-3 case switches when merging branches. Move the most likely condition to the front so it is checked first and the others can be skipped. This is currently not as effective as it could be because SimplifyCFG destroys profiling metadata when merging branches and switches. Merging branch weight metadata is tricky though. This code touches at most 3 cases so I didn't use a proper sorting algorithm. llvm-svn: 157521
* [NVPTX] Add a new test case for the newly-enabled call handlingJustin Holewinski2012-05-251-0/+26
| | | | | | NV_CONTRIB llvm-svn: 157485
* test/CodeGen/X86/bigstructret.ll: Suppress one test. It is ↵NAKAMURA Takumi2012-05-251-12/+0
| | | | | | msvc-incompatible. (compatible to mingw32 and netbsd, though) llvm-svn: 157474
* test/CodeGen/X86/bigstructret.ll: Relax stack offsets for hosts of ↵NAKAMURA Takumi2012-05-251-2/+2
| | | | | | stack-align=8, eg. win32 and netbsd. llvm-svn: 157471
* Simplify code for calling a function where CanLowerReturn fails, fixing a ↵Eli Friedman2012-05-251-6/+35
| | | | | | small bug in the process. llvm-svn: 157446
* Fix for CHECK-NOT misspelling.David Blaikie2012-05-241-1/+1
| | | | | | Patch by Nicklas Bo Jensen. llvm-svn: 157421
* Remove the PTX back-end and all of its artifacts (triple, etc.)Justin Holewinski2012-05-2430-2186/+0
| | | | | | | | This back-end was deprecated in favor of the NVPTX back-end. NV_CONTRIB llvm-svn: 157417
* Turn on mips16 pseudo op when compiling for mips16.Akira Hatanaka2012-05-241-0/+3
| | | | | | | | Expand test case for this. Patch by Reed Kotler. llvm-svn: 157410
* Enable Mips16 compiler to compile a null program.Akira Hatanaka2012-05-241-0/+10
| | | | | | | | First code from the Mips16 compiler. Includes trivial test program. Patch by Reed Kotler. llvm-svn: 157408
* Add a test case for global live range splitting.Jakob Stoklund Olesen2012-05-231-0/+27
| | | | llvm-svn: 157357
* Add a last resort tryInstructionSplit() to RAGreedy.Jakob Stoklund Olesen2012-05-231-0/+22
| | | | | | | | | | | | | Live ranges with a constrained register class may benefit from splitting around individual uses. It allows the remaining live range to use a larger register class where it may allocate. This is like spilling to a different register class. This is only attempted on constrained register classes. <rdar://problem/11438902> llvm-svn: 157354
* Correctly deal with identity copies in RegisterCoalescer.Jakob Stoklund Olesen2012-05-231-0/+82
| | | | | | | | | | | | | | | | | Now that the coalescer keeps live intervals and machine code in sync at all times, it needs to deal with identity copies differently. When merging two virtual registers, all identity copies are removed right away. This means that other identity copies must come from somewhere else, and they are going to have a value number. Deal with such copies by merging the value numbers before erasing the copy instruction. Otherwise, we leave dangling value numbers in the live interval. This fixes PR12927. llvm-svn: 157340
* [arm-fast-isel] Add support for non-global callee.Chad Rosier2012-05-231-0/+20
| | | | | | Patch by Jush Lu <jush.msn@gmail.com>. llvm-svn: 157336
* revert my previous patches that introduced an additional parameter to the ↵Nuno Lopes2012-05-227-31/+15
| | | | | | | | objectsize intrinsic. After a lot of discussion, we realized it's not the best option for run-time bounds checking llvm-svn: 157255
* Only erase virtregs with no uses left.Jakob Stoklund Olesen2012-05-221-0/+118
| | | | | | | | | Also make sure registers aren't erased twice if the dead def mentions the register twice. This fixes PR12911. llvm-svn: 157254
* FileCheck'ize test, and add a bit to test for r157221.Jim Grosbach2012-05-211-1/+7
| | | | llvm-svn: 157222
* Allow 256-bit shuffles to still be split even if only half of the shuffle ↵Craig Topper2012-05-211-6/+15
| | | | | | comes from two 128-bit pieces. llvm-svn: 157175
* When legalising shifts, do not pre-build a list of operands whichPeter Collingbourne2012-05-201-0/+18
| | | | | | | may be RAUW'd by the recursive call to LegalizeOps; instead, retrieve the other operands when calling UpdateNodeOperands. Fixes PR12889. llvm-svn: 157162
* Add a missing PPC 64-bit stwu pattern.Hal Finkel2012-05-201-0/+28
| | | | | | | This seems to fix the remaining compile-time failures on PPC64 when compiling with -enable-ppc-preinc. llvm-svn: 157159
* Use the right register class for LDRrs.Jakob Stoklund Olesen2012-05-201-2/+2
| | | | llvm-svn: 157152
* Transfer memory operands to the right instruction.Jakob Stoklund Olesen2012-05-201-4/+4
| | | | | | They need to go on the PICLDR as the verifier points out. llvm-svn: 157151
* Properly constrain register classes for sub-registers.Jakob Stoklund Olesen2012-05-201-2/+2
| | | | | | Not all GR64 registers have sub_8bit sub-registers. llvm-svn: 157150
* Properly constrain register classes in 2-addr.Jakob Stoklund Olesen2012-05-201-1/+1
| | | | | | | X86 has 2-addr instructions with different constraints on the tied def and use operands. One is GR32, one is GR32_NOSP. llvm-svn: 157149
* Fix 12892.Jakob Stoklund Olesen2012-05-191-0/+122
| | | | | | | | | | | | Dead code elimination during coalescing could cause a virtual register to be split into connected components. The following rewriting would be confused about the already joined copies present in the code, but without a corresponding value number in the live range. Erase all joined copies instantly when joining intervals such that the MI and LiveInterval representations are always in sync. llvm-svn: 157135
* Erase joined copies immediately.Jakob Stoklund Olesen2012-05-191-6/+6
| | | | | | | | | The late dead code elimination is no longer necessary. The test changes are cause by a register hint that can be either %rdi or %rax. The choice depends on the use list order, which this patch changes. llvm-svn: 157131
* On Haswell, perfer storing YMM registers using a single instruction.Nadav Rotem2012-05-191-0/+14
| | | | llvm-svn: 157129
* Add support for additional in-reg vbroadcast patternsNadav Rotem2012-05-191-0/+37
| | | | llvm-svn: 157127
* Add support for the 'd' mips inline asm output modifier.Eric Christopher2012-05-191-0/+6
| | | | | | Patch by Jack Carter. llvm-svn: 157093
* Refactor data-in-code annotations.Jim Grosbach2012-05-182-1/+45
| | | | | | | | | | | | | | | | | | | | | | Use a dedicated MachO load command to annotate data-in-code regions. This is the same format the linker produces for final executable images, allowing consistency of representation and use of introspection tools for both object and executable files. Data-in-code regions are annotated via ".data_region"/".end_data_region" directive pairs, with an optional region type. data_region_directive := ".data_region" { region_type } region_type := "jt8" | "jt16" | "jt32" | "jta32" end_data_region_directive := ".end_data_region" The previous handling of ARM-style "$d.*" labels was broken and has been removed. Specifically, it didn't handle ARM vs. Thumb mode when marking the end of the section. rdar://11459456 llvm-svn: 157062
* Add support for the mips 'x' inline asm modifier.Eric Christopher2012-05-181-0/+6
| | | | | | Patch by Jack Carter. llvm-svn: 157057
* Simplify handling of v16i8 shuffles and fix a missed optimization.Craig Topper2012-05-182-5/+6
| | | | llvm-svn: 157043
* Teach two-address pass to update the "source" map so it doesn't perform aEvan Cheng2012-05-181-0/+16
| | | | | | | | | non-profitable commute using outdated info. The test case would still fail because of poor pre-RA schedule. That will be fixed by MI scheduler. rdar://11472010 llvm-svn: 157038
* Remove a test that was only testing for physreg joining.Jakob Stoklund Olesen2012-05-181-12/+1
| | | | | | | | | | This is the same as the other tests: Clever tricks are required to make the arguments and return value line up in a single-instruction function. It rarely happens in real life. We have plenty other examples of this behavior. llvm-svn: 157030
* Remove -join-physregs from the test suite.Jakob Stoklund Olesen2012-05-1717-232/+227
| | | | | | | | | | | | | | This option has been disabled for a while, and it is going away so I can clean up the coalescer code. The tests that required physreg joining to be enabled were almost all of the form "tiny function with interference between arguments and return value". Such functions are usually inlined in the real world. The problem exposed by phys_subreg_coalesce-3.ll is real, but fairly rare. llvm-svn: 157027
* Remove incorrect pattern for ARM SMML instruction.Tim Northover2012-05-171-0/+13
| | | | | | Patch by Meador Inge. llvm-svn: 156989
* Avoid creating a cycle when folding load / op with flag / store. PR11451474. ↵Evan Cheng2012-05-161-0/+46
| | | | | | rdar://11451474 llvm-svn: 156896
* Enable sub-sub-register copy coalescing.Jakob Stoklund Olesen2012-05-151-0/+68
| | | | | | | | | | | | | | | | It is now possible to coalesce weird skewed sub-register copies by picking a super-register class larger than both original registers. The included test case produces code like this: vld2.32 {d16, d17, d18, d19}, [r0]! vst2.32 {d18, d19, d20, d21}, [r0] We still perform interference checking as if it were a normal full copy join, so this is still quite conservative. In particular, the f1 and f2 functions in the included test case still have remaining copies because of false interference. llvm-svn: 156878
* Enable all Hexagon tests.Sirish Pande2012-05-1511-28/+18
| | | | llvm-svn: 156824
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