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authorJakob Stoklund Olesen <stoklund@2pi.dk>2012-05-30 21:46:58 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2012-05-30 21:46:58 +0000
commit05e2245fc6485c6cdd32e45d25082b08ffe27074 (patch)
tree47d957db0a497218ecb87711387597faa19d3362 /llvm/test/CodeGen
parent7e6ad4627571cb1b744996f74c980d72a7ce74a4 (diff)
downloadbcm5719-llvm-05e2245fc6485c6cdd32e45d25082b08ffe27074.tar.gz
bcm5719-llvm-05e2245fc6485c6cdd32e45d25082b08ffe27074.zip
Prioritize smaller register classes for urgent evictions.
It helps compile exotic inline asm. In the test case, normal GR32 virtual registers use up eax-edx so the final GR32_ABCD live range has no registers left. Since all the live ranges were tiny, we had no way of prioritizing the smaller register class. This patch allows tiny unspillable live ranges to be evicted by tiny unspillable live ranges from a smaller register class. <rdar://problem/11542429> llvm-svn: 157715
Diffstat (limited to 'llvm/test/CodeGen')
-rw-r--r--llvm/test/CodeGen/X86/inline-asm.ll9
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/inline-asm.ll b/llvm/test/CodeGen/X86/inline-asm.ll
index eef6c2f377a..e6eb9efd8c7 100644
--- a/llvm/test/CodeGen/X86/inline-asm.ll
+++ b/llvm/test/CodeGen/X86/inline-asm.ll
@@ -43,3 +43,12 @@ entry:
%0 = tail call i8 asm sideeffect "xchg $0, $1", "=r,*m,0,~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %p, i1 %desired) nounwind
ret void
}
+
+; <rdar://problem/11542429>
+; The constrained GR32_ABCD register class of the 'q' constraint requires
+; special handling after the preceding outputs used up eax-edx.
+define void @constrain_abcd(i8* %h) nounwind ssp {
+entry:
+ %0 = call { i32, i32, i32, i32, i32 } asm sideeffect "", "=&r,=&r,=&r,=&r,=&q,r,~{ecx},~{memory},~{dirflag},~{fpsr},~{flags}"(i8* %h) nounwind
+ ret void
+}
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