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* ifcvt should ignore cfg where true and false successors are the same.Evan Cheng2009-06-151-0/+12
| | | | llvm-svn: 73423
* This test is failing. Revert for now.Bill Wendling2009-06-151-89/+0
| | | | llvm-svn: 73404
* Add another testcase for r71478.Bill Wendling2009-06-151-0/+89
| | | | llvm-svn: 73399
* CheckTailCallReturnConstraints is missing a check on theArnold Schwaighofer2009-06-151-0/+14
| | | | | | | | | incomming chain of the RETURN node. The incomming chain must be the outgoing chain of the CALL node. This causes the backend to identify tail calls that are not tail calls. This patch fixes this. llvm-svn: 73387
* Part 1.Evan Cheng2009-06-151-0/+14
| | | | | | | | | | | | | | | | | | | | | - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. llvm-svn: 73381
* Add a ARM specific pre-allocation pass that re-schedule loads / stores fromEvan Cheng2009-06-131-0/+13
| | | | | | | | | | | consecutive addresses togther. This makes it easier for the post-allocation pass to form ldm / stm. This is step 1. We are still missing a lot of ldm / stm opportunities because of register allocation are not done in the desired order. More enhancements coming. llvm-svn: 73291
* If killed register is defined by implicit_def, do not clear it since it's ↵Evan Cheng2009-06-121-0/+77
| | | | | | live range may overlap another def of same register. llvm-svn: 73255
* Mark some pattern-less instructions as neverHasSideEffects.Evan Cheng2009-06-121-1/+1
| | | | llvm-svn: 73252
* Fix Bug 4278: X86-64 with -tailcallopt calling conventionArnold Schwaighofer2009-06-122-6/+21
| | | | | | | | | | | | | | | out of sync with regular cc. The only difference between the tail call cc and the normal cc was that one parameter register - R9 - was reserved for calling functions through a function pointer. After time the tail call cc has gotten out of sync with the regular cc. We can use R11 which is also caller saved but not used as parameter register for potential function pointers and remove the special tail call cc on x86-64. llvm-svn: 73233
* Add testcase for register scanveger assertion fix in r72755Anton Korobeynikov2009-06-081-0/+8
| | | | | | (double def due to livevars) llvm-svn: 73096
* Fix the run-line for this test to work correctly outside of x86.Eli Friedman2009-06-071-1/+1
| | | | llvm-svn: 73025
* Tweak the expansion code for BIT_CONVERT to generate better code Eli Friedman2009-06-071-0/+10
| | | | | | converting from an MMX vector to an i64. llvm-svn: 73024
* Slightly generalize the code that handles shuffles of consecutive loads Eli Friedman2009-06-073-3/+14
| | | | | | | | | | | on x86 to handle more cases. Fix a bug in said code that would cause it to read past the end of an object. Rewrite the code in SelectionDAGLegalize::ExpandBUILD_VECTOR to be a bit more general. Remove PerformBuildVectorCombine, which is no longer necessary with these changes. In addition to simplifying the code, with this change, we can now catch a few more cases of consecutive loads. llvm-svn: 73012
* PR3628: Add patterns to match SHL/SRL/SRA to the corresponding Altivec Eli Friedman2009-06-071-0/+10
| | | | | | instructions. llvm-svn: 73009
* Fix the expansion for CONCAT_VECTORS so that it doesn't create illegal Eli Friedman2009-06-061-0/+8
| | | | | | types. llvm-svn: 72993
* Avoid crashing on a variable-index insertelement with element type i16.Eli Friedman2009-06-061-0/+11
| | | | llvm-svn: 72991
* Get rid of some bogus patterns for X86vzmovl. Don't create VZEXT_MOVL Eli Friedman2009-06-061-0/+37
| | | | | | | | nodes for vectors with an i16 element type. Add an optimization for building a vector which is all zeros/undef except for the bottom element, where the bottom element is an i8 or i16. llvm-svn: 72988
* Fix an obvious typo.Eli Friedman2009-06-061-1/+1
| | | | llvm-svn: 72987
* Get rid of a bogus pattern that interferes with optimization.Eli Friedman2009-06-061-0/+7
| | | | llvm-svn: 72985
* PR2598: make sure to expand illegal forms of integer/floating-point Eli Friedman2009-06-061-0/+13
| | | | | | | conversions for x86, like <2 x i32> -> <2 x float> and <4 x i16> -> <4 x float>. llvm-svn: 72983
* Adapt the x86 build_vector dagcombine to the current state of the legalizer.Nate Begeman2009-06-051-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | build vectors with i64 elements will only appear on 32b x86 before legalize. Since vector widening occurs during legalize, and produces i64 build_vector elements, the dag combiner is never run on these before legalize splits them into 32b elements. Teach the build_vector dag combine in x86 back end to recognize consecutive loads producing the low part of the vector. Convert the two uses of TLI's consecutive load recognizer to pass LoadSDNodes since that was required implicitly. Add a testcase for the transform. Old: subl $28, %esp movl 32(%esp), %eax movl 4(%eax), %ecx movl %ecx, 4(%esp) movl (%eax), %eax movl %eax, (%esp) movaps (%esp), %xmm0 pmovzxwd %xmm0, %xmm0 movl 36(%esp), %eax movaps %xmm0, (%eax) addl $28, %esp ret New: movl 4(%esp), %eax pmovzxwd (%eax), %xmm0 movl 8(%esp), %eax movaps %xmm0, (%eax) ret llvm-svn: 72957
* Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order ↵Evan Cheng2009-06-053-6/+4
| | | | | | change no longer make sense after the coalescing changes we have made since then. llvm-svn: 72955
* Fix an erroneous check for isFNeg; the FNeg case is handledDan Gohman2009-06-041-0/+7
| | | | | | a few lines later on. llvm-svn: 72904
* Split the Add, Sub, and Mul instruction opcodes into separateDan Gohman2009-06-04167-1473/+1473
| | | | | | | | | | | | | | | integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
* Add new function attribute - noredzone. Devang Patel2009-06-041-0/+9
| | | | | | | Update code generator to use this attribute and remove DisableRedZone target option. Update llc to set this attribute when -disable-red-zone command line option is used. llvm-svn: 72894
* RALinScan::attemptTrivialCoalescing() was returning a virtual register ↵Evan Cheng2009-06-041-0/+48
| | | | | | instead of the physical register it is allocated to. This resulted in virtual register(s) being added the live-in sets. llvm-svn: 72890
* A value defined by an implicit_def can be liven to a use BB. This is ↵Evan Cheng2009-06-041-0/+263
| | | | | | unfortunate. But register allocator still has to add it to the live-in set of the use BB. llvm-svn: 72888
* Check in test changes that I accidentally left out of r72872.Dan Gohman2009-06-041-0/+9
| | | | llvm-svn: 72875
* PR3739, part 2: Use an explicit store to spill XMM registers. (Previously,Eli Friedman2009-06-041-0/+12
| | | | | | the code tried to use "push", which doesn't exist for XMM registers.) llvm-svn: 72836
* PR3739, part 1: Disable the red zone on Win64.Eli Friedman2009-06-041-0/+9
| | | | llvm-svn: 72830
* Re-apply 72756 with fixes. One of those was introduced by we changed ↵Evan Cheng2009-06-041-1/+0
| | | | | | MachineInstrBuilder::addReg() interface. llvm-svn: 72826
* PR4317: Handle splits where the new block is unreachable correctly in Eli Friedman2009-06-031-0/+15
| | | | | | DominatorTreeBase::Split. llvm-svn: 72810
* For Darwin / x86_64, override -relocation-model=static to pic if the output ↵Evan Cheng2009-06-034-23/+3
| | | | | | | | is assembly since Darwin assembler does not really support -static codeine. I view this as a temporary workaround until the assembler / linker changes. llvm-svn: 72806
* Fix for PR4225: When rewriter reuse a value in a physical register , it ↵Evan Cheng2009-06-031-0/+362
| | | | | | clear the register kill operand marker and its kill ops information. However, the cleared operand may be a def of a super-register. Clear the kill ops info for the super-register's sub-registers as well. llvm-svn: 72758
* Temporarily revert 72756 for now.Evan Cheng2009-06-031-0/+1
| | | | llvm-svn: 72757
* Fold preceding / trailing base inc / dec into the single load / store as well.Evan Cheng2009-06-031-0/+12
| | | | llvm-svn: 72756
* Revert r72734. The Darwin assembler doesn't support the staticDan Gohman2009-06-033-4/+4
| | | | | | | relocation model on x86-64. Higher level logic should override the relocation model to PIC on x86_64-apple-darwin. llvm-svn: 72746
* Fix CodeGenPrepare's address-mode sinking to handle unusualDan Gohman2009-06-021-0/+24
| | | | | | | addresses, involving Base values which do not have Pointer type. This fixes PR4297. llvm-svn: 72739
* On Darwin x86_64 small code model doesn't guarantee code address fits in 32-bit.Evan Cheng2009-06-023-3/+13
| | | | llvm-svn: 72734
* (i64 (zext (srl GR32 8))) -> movzbl AH is not safe since srl 8 only clear ↵Evan Cheng2009-05-301-0/+28
| | | | | | the top 8 bits. llvm-svn: 72618
* Remove an accidental commit.Evan Cheng2009-05-291-40/+0
| | | | llvm-svn: 72560
* More h-registers tricks: folding zext nodes.Evan Cheng2009-05-292-0/+52
| | | | llvm-svn: 72558
* Do not try to create a MVT type of width 0.Evan Cheng2009-05-281-0/+38
| | | | llvm-svn: 72557
* Add explicit test for PR4280.Eli Friedman2009-05-281-0/+15
| | | | llvm-svn: 72539
* Add a testcase which got fixed by recent legalization work.Eli Friedman2009-05-281-0/+16
| | | | llvm-svn: 72517
* Added optimization that narrow load / op / store and the 'op' is a bit ↵Evan Cheng2009-05-282-0/+46
| | | | | | | | | | | | | twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code. e.g. orl $65536, 8(%rax) => orb $1, 10(%rax) Since narrowing is not always a win, e.g. i32 -> i16 is a loss on x86, dag combiner consults with the target before performing the optimization. llvm-svn: 72507
* This looks like it passes now.Bill Wendling2009-05-271-1/+0
| | | | llvm-svn: 72485
* Fix PR4254.Torok Edwin2009-05-231-0/+14
| | | | | | | | | | | The DAGCombiner created a negative shiftamount, stored in an unsigned variable. Later the optimizer eliminated the shift entirely as being undefined. Example: (srl (shl X, 56) 48). ShiftAmt is 4294967288. Fix it by checking that the shiftamount is positive, and storing in a signed variable. llvm-svn: 72331
* available_externall linkage is not local, this was confusing the codegenerator,Torok Edwin2009-05-231-0/+19
| | | | | | | | | and it wasn't generating calls through @PLT for these functions. hasLocalLinkage() is now false for available_externally, I attempted to fix the inliner and dce to handle available_externally properly. It passed make check. llvm-svn: 72328
* Fix test to account for legalization changes; I think this ends up Eli Friedman2009-05-231-1/+1
| | | | | | running an extra DAGCombine pass which improves the code a bit. llvm-svn: 72326
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