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* Reapply 91904.Sanjiv Gupta2009-12-231-0/+15
| | | | llvm-svn: 91996
* deleting empty file.Sanjiv Gupta2009-12-231-0/+0
| | | | llvm-svn: 91994
* Reverting back 91904.Sanjiv Gupta2009-12-231-15/+0
| | | | llvm-svn: 91993
* Use more sensible type for flags in asms. PR 5570.Dale Johannesen2009-12-231-0/+29
| | | | | | Patch by Sylve`re Teissier (sorry, ASCII only). llvm-svn: 91988
* Update objectsize intrinsic and associated dependencies. FixEric Christopher2009-12-231-4/+4
| | | | | | lowering code and update testcases. llvm-svn: 91979
* Add testcase for PR5703Anton Korobeynikov2009-12-221-0/+13
| | | | llvm-svn: 91931
* Remove target attribute break-sse-dep. Instead, do not fold load into sse ↵Evan Cheng2009-12-221-14/+7
| | | | | | partial update instructions unless optimizing for size. llvm-svn: 91910
* While converting one of the operands to a memory operand, we need to check ↵Sanjiv Gupta2009-12-221-0/+15
| | | | | | if it is Legal and does not result into a cyclic dep. llvm-svn: 91904
* Emit direction operand in binary insns that stores in memory.Sanjiv Gupta2009-12-191-0/+13
| | | | llvm-svn: 91777
* Test cases for changes done in 91768.Sanjiv Gupta2009-12-192-0/+21
| | | | llvm-svn: 91773
* Increase opportunities to optimize (brcond (srl (and c1), c2)).Evan Cheng2009-12-181-0/+29
| | | | llvm-svn: 91717
* On recent Intel u-arch's, folding loads into some unary SSE instructions canEvan Cheng2009-12-181-0/+28
| | | | | | | | | | | | | | | | | | | be non-optimal. To be precise, we should avoid folding loads if the instructions only update part of the destination register, and the non-updated part is not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks the partial register dependency and it can improve performance. e.g. movss (%rdi), %xmm0 cvtss2sd %xmm0, %xmm0 instead of cvtss2sd (%rdi), %xmm0 An alternative method to break dependency is to clear the register first. e.g. xorps %xmm0, %xmm0 cvtss2sd (%rdi), %xmm0 llvm-svn: 91672
* Tidy up this testcase and add test for tailcall optimizationDan Gohman2009-12-181-7/+12
| | | | | | with unreachable. llvm-svn: 91650
* Handle ARM inline asm "w" constraints with 64-bit ("d") registers.Bob Wilson2009-12-181-0/+12
| | | | | | | | The change in SelectionDAGBuilder is needed to allow using bitcasts to convert between f64 (the default type for ARM "d" registers) and 64-bit Neon vector types. Radar 7457110. llvm-svn: 91649
* Remove "tail" keywords. These calls are not intended to be tail calls.Dan Gohman2009-12-181-33/+33
| | | | | | | This protects this test from depending on codegen not performing the tail call optimization by default. llvm-svn: 91648
* Add test case for the phi reuse patch.Jakob Stoklund Olesen2009-12-181-0/+66
| | | | llvm-svn: 91642
* Instruction fixes, added instructions, and AsmString changes in theSean Callanan2009-12-1815-197/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
* Revert this dag combine change:Evan Cheng2009-12-171-4/+4
| | | | | | | | Fold (zext (and x, cst)) -> (and (zext x), cst) DAG combiner likes to optimize expression in the other way so this would end up cause an infinite looping. llvm-svn: 91574
* Make this test pass on Linux.Nick Lewycky2009-12-161-9/+20
| | | | llvm-svn: 91521
* Re-enable 91381 with fixes.Evan Cheng2009-12-161-1/+0
| | | | llvm-svn: 91489
* Do better with physical reg operands (typically, from inline asm)Dale Johannesen2009-12-162-2/+51
| | | | | | | | | | | | | | | | | | in local register allocator. If a reg-reg copy has a phys reg input and a virt reg output, and this is the last use of the phys reg, assign the phys reg to the virt reg. If a reg-reg copy has a phys reg output and we need to reload its spilled input, reload it directly into the phys reg than passing it through another reg. Following 76208, there is sometimes no dependency between the def of a phys reg and its use; this creates a window where that phys reg can be used for spilling (this is true in linear scan also). This is bad and needs to be fixed a better way, although 76208 works too well in practice to be reverted. However, there should normally be no spilling within inline asm blocks. The patch here goes a long way towards making this actually be true. llvm-svn: 91485
* For fastcc on x86, let ECX be used as a return register after EAX and EDXKenneth Uildriks2009-12-151-0/+15
| | | | llvm-svn: 91410
* Disable 91381 for now. It's miscompiling ARMISelDAG2DAG.cpp.Evan Cheng2009-12-151-0/+1
| | | | llvm-svn: 91405
* Make 91378 more conservative.Evan Cheng2009-12-151-13/+0
| | | | | | | 1. Only perform (zext (shl (zext x), y)) -> (shl (zext x), y) when y is a constant. This makes sure it remove at least one zest. 2. If the shift is a left shift, make sure the original shift cannot shift out bits. llvm-svn: 91399
* Use sbb x, x to materialize carry bit in a GPR. The result is all one's or ↵Evan Cheng2009-12-151-0/+23
| | | | | | all zero's. llvm-svn: 91381
* Fold (zext (and x, cst)) -> (and (zext x), cst).Evan Cheng2009-12-151-4/+4
| | | | llvm-svn: 91380
* Propagate zest through logical shift.Evan Cheng2009-12-152-0/+51
| | | | llvm-svn: 91378
* Fix integer cast code to handle vector types.Dan Gohman2009-12-141-0/+13
| | | | llvm-svn: 91362
* Disable r91104 for x86. It causes partial register stall which pessimize ↵Evan Cheng2009-12-121-1/+3
| | | | | | code in 32-bit. llvm-svn: 91223
* Lower setcc branchless, if this is profitable.Anton Korobeynikov2009-12-111-0/+116
| | | | | | Based on the patch by Brian Lucas! llvm-svn: 91175
* Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.Dan Gohman2009-12-111-0/+37
| | | | llvm-svn: 91158
* Change this to the correct PR number.Dan Gohman2009-12-111-1/+1
| | | | llvm-svn: 91148
* Fix the result type of SELECT nodes lowered from Select instructions withDan Gohman2009-12-111-0/+15
| | | | | | aggregate return values. This fixes PR5754. llvm-svn: 91145
* Honour setHasCalls() set from isel.Anton Korobeynikov2009-12-111-0/+63
| | | | | | | This is used in some weird cases like general dynamic TLS model. This fixes PR5723 llvm-svn: 91144
* Tests for 91103 and 91104.Evan Cheng2009-12-111-0/+93
| | | | llvm-svn: 91105
* It's not safe to coalesce a move where src and dst registers have different ↵Evan Cheng2009-12-101-0/+40
| | | | | | | | subregister indices. e.g.: %reg16404:1<def> = MOV8rr %reg16412:2<kill> llvm-svn: 91061
* Fix test.Evan Cheng2009-12-091-1/+1
| | | | llvm-svn: 90988
* Optimize splat of a scalar load into a shuffle of a vector load when it's ↵Evan Cheng2009-12-091-0/+43
| | | | | | | | | | | | legal. e.g. vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0> => vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1> iff ptr is 16-byte aligned (or can be made into 16-byte aligned). llvm-svn: 90984
* Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 ↵Evan Cheng2009-12-091-3/+3
| | | | | | isl lowering code. llvm-svn: 90925
* - Support inline asm 'w' constraint for 128-bit vector types.Evan Cheng2009-12-081-0/+13
| | | | | | - Also support the 'q' NEON registers asm code. llvm-svn: 90894
* Reduce (cmp 0, and_su (foo, bar)) into (bit foo, bar). This saves extra ↵Anton Korobeynikov2009-12-081-0/+166
| | | | | | instruction. Patch inspired by Brian Lucas! llvm-svn: 90819
* Use FileCheck and set nounwind on calls.David Greene2009-12-071-6/+7
| | | | llvm-svn: 90790
* Don't enable the post-RA scheduler on x86 except at -O3. In itsDan Gohman2009-12-078-8/+8
| | | | | | current form, it is too expensive in compile time. llvm-svn: 90781
* Dynamic stack realignment use of sp register as source/dest registerAnton Korobeynikov2009-12-062-2/+2
| | | | | | | | | | in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode. Emit the following code instead: mov r4, sp bic r4, r4, #15 mov sp, r4 llvm-svn: 90724
* Temporarily revert r90502. It was causing the llvm-gcc bootstrap on PPC to fail.Bill Wendling2009-12-052-2/+2
| | | | llvm-svn: 90653
* Also attempt trivial coalescing for live intervals that end in a copy.Jakob Stoklund Olesen2009-12-042-2/+2
| | | | | | | | | | | | | The coalescer is supposed to clean these up, but when setting up parameters for a function call, there may be copies to physregs. If the defining instruction has been LICM'ed far away, the coalescer won't touch it. The register allocation hint does not always work - when the register allocator is backtracking, it clears the hints. This patch takes care of a few more cases that r90163 missed. llvm-svn: 90502
* Don't pull vector sext through both hands of a logical operation, since ↵Nate Begeman2009-12-031-0/+29
| | | | | | | | | doing so prevents the fusion of vector sext and setcc into vsetcc. Add a testcase for the above transformation. Fix a bogus use of APInt noticed while tracking this down. llvm-svn: 90423
* Recognize canonical forms of vector shuffles where the same vector is used forBob Wilson2009-12-031-0/+19
| | | | | | | | both source operands. In the canonical form, the 2nd operand is changed to an undef and the shuffle mask is adjusted to only reference elements from the 1st operand. Radar 7434842. llvm-svn: 90417
* Remove unnecessary check.Bill Wendling2009-12-021-1/+0
| | | | llvm-svn: 90352
* Fix PR5391: support early clobber physical register def tied with a use (ewwww)Evan Cheng2009-12-011-0/+38
| | | | | | | | - A valno should be set HasRedefByEC if there is an early clobber def in the middle of its live ranges. It should not be set if the def of the valno is defined by an early clobber. - If a physical register def is tied to an use and it's an early clobber, it just means the HasRedefByEC is set since it's still one continuous live range. - Add a couple of missing checks for HasRedefByEC in the coalescer. In general, it should not coalesce a vr with a physical register if the physical register has a early clobber def somewhere. This is overly conservative but that's the price for using such a nasty inline asm "feature". llvm-svn: 90269
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