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* Broaden isSchedulingBoundary to check aliases of SP.Andrew Trick2012-11-171-0/+33
| | | | | | | | On PPC the stack pointer is X1, but ADJCALLSTACK writes R1. Fixes PR14315: Register regmask dependency problem with misched. llvm-svn: 168248
* Mark FP_EXTEND form v2f32 to v2f64 as "expand" for ARM NEON. Patch by Pete ↵Eli Friedman2012-11-171-0/+8
| | | | | | Couperus. llvm-svn: 168240
* [fast-isel] Add the -verify-machineinstrs to these test cases. The remainingChad Rosier2012-11-178-15/+15
| | | | | | | test cases require fixes to fast-isel before the verifier can be enabled. Part of rdar://12594152 llvm-svn: 168233
* Initial implementation of MipsTargetLowering::isLegalAddressingMode.Akira Hatanaka2012-11-171-0/+41
| | | | llvm-svn: 168230
* Remove hard coded registers in ARM ldrexd and strexd instructionsWeiming Zhao2012-11-161-41/+41
| | | | | | | | | This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
* Make sure FABS on v2f32 and v4f32 is legal on ARM NEONAnton Korobeynikov2012-11-161-0/+17
| | | | | | This fixes PR14359 llvm-svn: 168200
* Fix handling of aliases to functions.Richard Osborne2012-11-161-0/+32
| | | | | | An alias to a function should use pc relative addressing. llvm-svn: 168199
* [NVPTX] Order global variables in def-use order before emiting them in the ↵Justin Holewinski2012-11-161-0/+20
| | | | | | final assembly llvm-svn: 168198
* llvm/test/CodeGen/X86/hipe-cc*.ll: Add explicit -mcpu, or they don't expect ↵NAKAMURA Takumi2012-11-162-2/+2
| | | | | | to pass on Atom. llvm-svn: 168171
* Add the Erlang/HiPE calling convention, patch by Yiannis Tsiouris.Duncan Sands2012-11-162-0/+164
| | | | llvm-svn: 168166
* Use roundps/pd for llvm.ceil, llvm.trunc, llvm.rint, and llvm.nearbyint of ↵Craig Topper2012-11-161-0/+144
| | | | | | vector types. llvm-svn: 168141
* [mips] Fix delay slot filler so that instructions with register operand $1 areAkira Hatanaka2012-11-161-0/+32
| | | | | | allowed in branch delay slot. llvm-svn: 168131
* Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missingEli Friedman2012-11-151-0/+9
| | | | | | | | case to vector legalization so this actually works. Patch by Pete Couperus. Fixes PR12540. llvm-svn: 168107
* PowerPC: Lowering floor intrinsic for AltivecAdhemerval Zanella2012-11-151-0/+172
| | | | | | | | This patch lowers the llvm.floor, llvm.ceil, llvm.trunc, and llvm.nearbyint to Altivec instruction when using 4 single-precision float vectors. llvm-svn: 168086
* This patch is in preparation for adding medium code model support to theBill Schmidt2012-11-144-4/+4
| | | | | | | | | | | | | | PPC64 target. The five tests modified herein test code generation that is sensitive to the code model selected. So I've added -code-model=small to the RUN commands for each. Since small code model is the default, this has no effect for now; but this prepares us for eventually changing the default to medium code model for PPC64. Test changes verified with small and medium code model as default on powerpc64-unknown-linux-gnu. All tests continue to pass. llvm-svn: 167999
* Make sure to not get AVX code on an AVX-capable host. Revealed in r167967.Jakub Staszak2012-11-144-8/+8
| | | | llvm-svn: 167989
* test/CodeGen/Hexagon/postinc-load.ll: Suppress it for now. It triggered the ↵NAKAMURA Takumi2012-11-141-1/+1
| | | | | | failure on i686 hosts. llvm-svn: 167988
* Remove the CellSPU port.Eric Christopher2012-11-1459-7313/+0
| | | | | | Approved by Chris Lattner. llvm-svn: 167984
* llvm/test/CodeGen/X86/memset.ll: FileCheck-ize, and add another case on +avx.NAKAMURA Takumi2012-11-141-2/+23
| | | | llvm-svn: 167975
* Added multiclass for post-increment load instructions.Jyotsna Verma2012-11-141-0/+29
| | | | llvm-svn: 167974
* Force CPU in test so we don't accidentally get AVX code on an AVX-capable host.Benjamin Kramer2012-11-141-2/+2
| | | | llvm-svn: 167973
* X86: Enable SSE memory intrinsics even when stack alignment is less than 16 ↵Benjamin Kramer2012-11-144-22/+79
| | | | | | | | | | | | | | | | | | bytes. The stack realignment code was fixed to work when there is stack realignment and a dynamic alloca is present so this shouldn't cause correctness issues anymore. Note that this also enables generation of AVX instructions for memset under the assumptions: - Unaligned loads/stores are always fast on CPUs supporting AVX - AVX is not slower than SSE We may need some tweaked heuristics if one of those assumptions turns out not to be true. Effectively reverts r58317. Part of PR2962. llvm-svn: 167967
* The code pattern "imm0_255_neg" is used for checking if an immediate value ↵Nadav Rotem2012-11-141-0/+31
| | | | | | | | | | | is a small negative number. This patch changes the definition of negative from -0..-255 to -1..-255. I am changing this because of a bug that we had in some of the patterns that assumed that "subs" of zero does not set the carry flag. rdar://12028498 llvm-svn: 167963
* [NVPTX] Implement custom lowering of loads/stores for i1Justin Holewinski2012-11-141-0/+26
| | | | | | | | | Loads from i1 become loads from i8 followed by trunc Stores to i1 become zext to i8 followed by store to i8 Fixes PR13291 llvm-svn: 167948
* Fix really stupid ARM EHABI info generation bug: we should not emitAnton Korobeynikov2012-11-141-0/+18
| | | | | | | eh table and handler data if there are no landing pads in the function. Patch by Logan Chien with some cleanups from me. llvm-svn: 167945
* Handle DAG CSE adding new uses during ReplaceAllUsesWith. Fixes PR14333.Rafael Espindola2012-11-141-0/+12
| | | | llvm-svn: 167912
* Use TARGET2 relocation for TType references on ARM.Anton Korobeynikov2012-11-141-0/+44
| | | | | | | | Do some cleanup of the code while here. Inspired by patch by Logan Chien! llvm-svn: 167904
* Revert "Use the 'count' attribute instead of the 'upper_bound' attribute."Eric Christopher2012-11-131-2/+2
| | | | | | | | temporarily as it is breaking the gdb bots. This reverts commit r167806/e7ff4c14b157746b3e0228d2dce9f70712d1c126. llvm-svn: 167886
* X86: when constructing VZEXT_LOAD from other loads, makes sure its outputManman Ren2012-11-131-0/+51
| | | | | | | | | | | chain is correctly setup. As an example, if the original load must happen before later stores, we need to make sure the constructed VZEXT_LOAD is constrained to be before the stores. rdar://12684358 llvm-svn: 167859
* Do not consider a machine instruction that uses and defines the sameUlrich Weigand2012-11-131-0/+18
| | | | | | | | | | physical register as candidate for common subexpression elimination in MachineCSE. This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc caused by MachineCSE invalidly merging two separate DYNALLOC insns. llvm-svn: 167855
* Codegen support for arbitrary vector getelementptrs.Duncan Sands2012-11-131-0/+5
| | | | llvm-svn: 167830
* Use the 'count' attribute instead of the 'upper_bound' attribute.Bill Wendling2012-11-131-2/+2
| | | | | | | | | If we have a type 'int a[1]' and a type 'int b[0]', the generated DWARF is the same for both of them because we use the 'upper_bound' attribute. Instead use the 'count' attrbute, which gives the correct number of elements in the array. <rdar://problem/12566646> llvm-svn: 167806
* Cleanup the main RegisterCoalescer loop.Andrew Trick2012-11-131-1/+1
| | | | | | Block priorities still apply outside loops. llvm-svn: 167793
* Fix test case added in patch fixing PR14314Michael Liao2012-11-121-4/+4
| | | | llvm-svn: 167769
* misched: Infrastructure for weak DAG edges.Andrew Trick2012-11-121-0/+2
| | | | | | | | This adds support for weak DAG edges to the general scheduling infrastructure in preparation for MachineScheduler support for heuristics based on weak edges. llvm-svn: 167738
* Fix PR14314Michael Liao2012-11-122-4/+17
| | | | | | | - Fix operand order for atomic sub, where the minuend is the value loaded from memory and the subtrahend is the parameter specified. llvm-svn: 167718
* [NVPTX] Add more precise PTX/SM target attributesJustin Holewinski2012-11-1210-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each SM and PTX version is modeled as a subtarget feature/CPU. Additionally, PTX 3.1 is added as the default PTX version to be out-of-the-box compatible with CUDA 5.0. Available CPUs for this target: sm_10 - Select the sm_10 processor. sm_11 - Select the sm_11 processor. sm_12 - Select the sm_12 processor. sm_13 - Select the sm_13 processor. sm_20 - Select the sm_20 processor. sm_21 - Select the sm_21 processor. sm_30 - Select the sm_30 processor. sm_35 - Select the sm_35 processor. Available features for this target: ptx30 - Use PTX version 3.0. ptx31 - Use PTX version 3.1. sm_10 - Target SM 1.0. sm_11 - Target SM 1.1. sm_12 - Target SM 1.2. sm_13 - Target SM 1.3. sm_20 - Target SM 2.0. sm_21 - Target SM 2.1. sm_30 - Target SM 3.0. sm_35 - Target SM 3.5. llvm-svn: 167699
* Convert an improper CodeGen test to a MC test.Evan Cheng2012-11-101-25/+0
| | | | llvm-svn: 167663
* xfail a bad test. This is a MC test but it's dependent on a codegen ↵Evan Cheng2012-11-101-0/+2
| | | | | | optimization which is now disabled. llvm-svn: 167658
* Disable the Thumb no-return call optimization:Evan Cheng2012-11-102-15/+0
| | | | | | | | | | | | mov lr, pc b.w _foo The "mov" instruction doesn't set bit zero to one, it's putting incorrect value in lr. It messes up backtraces. rdar://12663632 llvm-svn: 167657
* Cleanup pcmp(e/i)str(m/i) instruction definitions and load folding support.Craig Topper2012-11-101-5/+47
| | | | llvm-svn: 167652
* [NVPTX] Use ABI alignment for parameters when alignment is not specified.Justin Holewinski2012-11-091-0/+25
| | | | | | Affects SM 2.0+. Fixes bug 13324. llvm-svn: 167646
* Fix assertions in updateRegMaskSlots().Jakob Stoklund Olesen2012-11-091-0/+45
| | | | | | | | | The RegMaskSlots contains 'r' slots while NewIdx and OldIdx are 'B' slots. This broke the checks in the assertions. This fixes PR14302. llvm-svn: 167625
* Recommit modified r167540.Amara Emerson2012-11-081-2/+2
| | | | | | | Improve ARM build attribute emission for architectures types. This also changes the default architecture emitted for a generic CPU to "v7". llvm-svn: 167574
* Add support of RTM from TSX extensionMichael Liao2012-11-081-0/+30
| | | | | | | | - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region llvm-svn: 167573
* [mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node.Akira Hatanaka2012-11-071-0/+63
| | | | | | Patch by Sasa Stankovic. llvm-svn: 167548
* misched: Heuristics based on the machine model.Andrew Trick2012-11-071-0/+230
| | | | | | | | | | | | | | misched is disabled by default. With -enable-misched, these heuristics balance the schedule to simultaneously avoid saturating processor resources, expose ILP, and minimize register pressure. I've been analyzing the performance of these heuristics on everything in the llvm test suite in addition to a few other benchmarks. I would like each heuristic check to be verified by a unit test, but I'm still trying to figure out the best way to do that. The heuristics are still in considerable flux, but as they are refined we should be rigorous about unit testing the improvements. llvm-svn: 167527
* On PowerPC64, integer return values (as well as arguments) are supposedUlrich Weigand2012-11-052-1/+99
| | | | | | | | | | | | | | | | | | | | | | | | | to be extended to a full register. This is modeled in the IR by marking the return value (or argument) with a signext or zeroext attribute. However, while these attributes are respected for function arguments, they are currently ignored for function return values by the PowerPC back-end. This patch updates PPCCallingConv.td to ask for the promotion to i64, and fixes LowerReturn and LowerCallResult to implement it. The new test case verifies that both arguments and return values are properly extended when passing them; and also that the optimizers understand incoming argument and return values are in fact guaranteed by the ABI to be extended. The patch caused a spurious breakage in CodeGen/PowerPC/coalesce-ext.ll, since the test case used a "ret" instruction to create a use of an i32 value at the end of the function (to set up data flow as required for what the test is intended to test). Since there's now an implicit promotion to i64, that data flow no longer works as expected. To fix this, this patch now adds an extra "add" to ensure we have an appropriate use of the i32 value. llvm-svn: 167396
* Add support for the PowerPC-specific inline asm Z constraint and y modifier.Hal Finkel2012-11-051-0/+14
| | | | | | | | | | The Z constraint specifies an r+r memory address, and the y modifier expands to the "r, r" in the asm string. For this initial implementation, the base register is forced to r0 (which has the special meaning of 0 for r+r addressing on PowerPC) and the full address is taken in the second register. In the future, this should be improved. llvm-svn: 167388
* [PATCH] PowerPC: Expand load extend vector operationsAdhemerval Zanella2012-11-051-0/+155
| | | | | | | This patch expands the SEXTLOAD, ZEXTLOAD, and EXTLOAD operations for vector types when altivec is enabled. llvm-svn: 167386
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