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* Revert "StructurizeCFG: Test for branch divergence correctly"Adam Nemet2018-02-241-2/+2
| | | | | | | | This reverts commit r325881. Breaks many bots llvm-svn: 326037
* [X86][SSE] combineSubToSubus - support v8i64 handling from SSSE3Simon Pilgrim2018-02-241-241/+163
| | | | | | Our UMIN/UMAX, vector truncation and shuffle combining is good enough to efficiently handle v8i64 with the number of leading zeros that are necessary for PSUBUS. llvm-svn: 326034
* [X86][SSE] combineSubToSubus - support v8i32 handling from SSSE3 (not SSE41)Simon Pilgrim2018-02-241-77/+54
| | | | | | Now that UMIN etc are Legal/Custom for SSE2+, we can efficiently match SUBUS v8i32 cases from SSSE3 which can perform efficient truncation with PSHUFB. llvm-svn: 326033
* [X86][SSE] combineSubToSubus - begun generalizing to work with any type ↵Simon Pilgrim2018-02-241-14/+14
| | | | | | sizes with SplitBinaryOpsAndApply llvm-svn: 326030
* [Sparc] Return true in enableMultipleCopyHints().Jonas Paulsson2018-02-243-33/+23
| | | | | | | | | | Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: James Y Knight llvm-svn: 326028
* [AMDGPU] Shrinking V_SUBBREV_U32Stanislav Mekhanoshin2018-02-242-6/+6
| | | | | | | | | | V_SUBBREV_U32 is a commute opcode for V_SUBB_U32. However, when we try to commute V_SUBB_U32 in order to shrink it we do not then process V_SUBBREV_U32 and it stay VOP3. This is fixed. Differential Revision: https://reviews.llvm.org/D43699 llvm-svn: 326011
* [X86] Remove checks for '(scalar_to_vector (i8 (trunc GR32:)))' from scalar ↵Craig Topper2018-02-241-10/+4
| | | | | | | | masked move patterns. This portion can be matched by other patterns. We don't need it to make the larger pattern valid. It's sufficient to have a v1i1 mask input without caring where it came from. llvm-svn: 325999
* [AMDGPU] Fixed madak.ll test on VI, added GFX10. NFC.Stanislav Mekhanoshin2018-02-231-33/+45
| | | | llvm-svn: 325995
* bpf: New codegen testcases for 32-bit subregister supportYonghong Song2018-02-234-0/+541
| | | | | | | | | | This patch adds some unit tests for 32-bit subregister support. We want to make sure ALU32, subregister load/store and new peephole optimization are truely enabled once -mattr=+alu32 specified. Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325992
* [DebugInfo] Add remaining files to r325970Scott Linder2018-02-231-0/+61
| | | | | | Add files which I missed in the original check-in llvm-svn: 325973
* [PowerPC] Disable shrink-wrapping when getting PC address through the LRNemanja Ivanovic2018-02-231-0/+70
| | | | | | | | | | | | | | The instruction sequence used to get the address of the PC into a GPR requires that we clobber the link register. Doing so without having first saved it in the prologue leaves the function unable to return. Currently, this sequence is emitted into the entry block. To ensure the prologue is inserted before this sequence, disable shrink-wrapping. This fixes PR33547. Differential Revision: https://reviews.llvm.org/D43677 llvm-svn: 325972
* [DebugInfo] Support DWARF v5 source code embedding extensionScott Linder2018-02-233-11/+21
| | | | | | | | | | | | | | | | | | | In DWARF v5 the Line Number Program Header is extensible, allowing values with new content types. In this extension a content type is added, DW_LNCT_LLVM_source, which contains the embedded source code of the file. Add new optional attribute for !DIFile IR metadata called source which contains source text. Use this to output the source to the DWARF line table of code objects. Analogously extend METADATA_FILE in Bitcode and .file directive in ASM to support optional source. Teach llvm-dwarfdump and llvm-objdump about the new values. Update the output format of llvm-dwarfdump to make room for the new attribute on file_names entries, and support embedded sources for the -source option in llvm-objdump. Differential Revision: https://reviews.llvm.org/D42765 llvm-svn: 325970
* Intrinsics calls should avoid the PLT when "RtLibUseGOT" metadata is present.Sriraman Tallam2018-02-231-0/+17
| | | | | | Differential Revision: https://reviews.llvm.org/D42216 llvm-svn: 325962
* [Hexagon] Recognize non-immediate constants in HexagonConstPropagationKrzysztof Parzyszek2018-02-231-0/+25
| | | | llvm-svn: 325954
* [X86] Add DAG combine to remove (and X, 1) from in front of a v1i1 scalar to ↵Craig Topper2018-02-231-4/+2
| | | | | | | | | | | | vector. These can be created by type legalization promoting the inputs to select to match scalar boolean contents. We were trying to pattern match them away during isel, but its better to just remove them from the DAG. I've cleaned up some patterns to not check for this 'and' anymore. But I suspect this has also opened up opportunities for pattern removal. llvm-svn: 325949
* [X86][SSE] Generalize x > C-1 ? x+-C : 0 --> subus x, C combine for ↵Simon Pilgrim2018-02-231-93/+19
| | | | | | non-uniform constants llvm-svn: 325944
* [PATCH] [AArch64] Add new target feature to fuse conditional selectEvandro Menezes2018-02-231-0/+30
| | | | | | | | | This feature enables the fusion of the comparison and the conditional select instructions together. Differential revision: https://reviews.llvm.org/D42392 llvm-svn: 325939
* [X86][SSE] Add x > C-1 ? x+-C : 0 --> subus x, C test caaes for non-uniform ↵Simon Pilgrim2018-02-231-0/+136
| | | | | | constants llvm-svn: 325936
* [X86] Custom split v32i16/v64i8 bitcasts when AVX512F is available, but BWI ↵Craig Topper2018-02-231-2122/+106
| | | | | | | | | | is not. The test changes you can see are related to the changes in ReplaceNodeResults. Though shuffle-vs-trunc-512.ll does have a test that exercises the code in LowerBITCAST. Looks like the test output didn't change because DAG combining is able to clean up the resulting type legalization. Adding the custom hook just makes type legalization work less hard. Differential Revision: https://reviews.llvm.org/D43447 llvm-svn: 325933
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-231-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931
* [X86] Regenerate i128 multiply testsSimon Pilgrim2018-02-231-14/+348
| | | | llvm-svn: 325919
* Support for the mno-stack-arg-probe flagHans Wennborg2018-02-231-0/+38
| | | | | | | | | | | | Adds support for this flag. There is also another piece for clang (separate review). More info: https://bugs.llvm.org/show_bug.cgi?id=36221 By Ruslan Nikolaev! Differential Revision: https://reviews.llvm.org/D43107 llvm-svn: 325900
* [SystemZ] Also update the CHECK line for VPDIJonas Paulsson2018-02-231-1/+1
| | | | llvm-svn: 325898
* [SystemZ] Fix VPDI argument in test.Jonas Paulsson2018-02-231-1/+1
| | | | | | To select element 1 from each half with VPDI, a constant of 5 should be used. llvm-svn: 325897
* [X86][F16C] Regenerate half conversion testsSimon Pilgrim2018-02-231-133/+133
| | | | llvm-svn: 325896
* [DAGCOmbine] Ensure that (brcond (setcc ...)) is handled in a canonical manner.Amaury Sechet2018-02-235-33/+21
| | | | | | | | | | | | | | | Summary: There are transformation that change setcc into other constructs, and transform that try to reconstruct a setcc from the brcond condition. Depending on what order these transform are done, the end result differs. Most of the time, it is preferable to get a setcc as a brcond argument (and this is why brcond try to recreate the setcc in the first place) so we ensure this is done every time by also doing it at the setcc level when the only user is a brcond. Reviewers: spatel, hfinkel, niravd, craig.topper Subscribers: nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D41235 llvm-svn: 325892
* [MIPS GlobalISel] Adding GlobalISelPetar Jovanovic2018-02-232-0/+23
| | | | | | | | | | | Add GlobalISel infrastructure up to the point where we can select a ret void. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D43583 llvm-svn: 325888
* AMDGPU: Track physreg uses in SILoadStoreOptimizerNicolai Haehnle2018-02-233-10/+158
| | | | | | | | | | | | | | | | Summary: This handles def-after-use of physregs, and allows us to merge loads and stores even across some physreg defs (typically M0 defs). Change-Id: I076484b2bda27c2cf46013c845a0380c5b89b67b Reviewers: arsenm, mareko, rampitec Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D42647 llvm-svn: 325882
* StructurizeCFG: Test for branch divergence correctlyNicolai Haehnle2018-02-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | Summary: This fixes cases like the new test @nonuniform. In that test, %cc itself is a uniform value; however, when reading it after the end of the loop in basic block %if, its value is effectively non-uniform. This problem was encountered in https://bugs.freedesktop.org/show_bug.cgi?id=103743; however, this change in itself is not sufficient to fix that bug, as there is another issue in the AMDGPU backend. Change-Id: I32bbffece4a32f686fab54964dae1a5dd72949d4 Reviewers: arsenm, rampitec, jlebar Subscribers: wdng, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D40546 llvm-svn: 325881
* [Mips] Return true in enableMultipleCopyHints().Jonas Paulsson2018-02-237-479/+491
| | | | | | | | | | Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
* Remove file missed by r325852 due to merge conflict.Richard Smith2018-02-231-1378/+0
| | | | llvm-svn: 325853
* Revert r325128 ("[X86] Reduce Store Forward Block issues in HW").Richard Smith2018-02-231-1926/+0
| | | | | | This is causing miscompiles in some situations. See the llvm-commits thread for the commit for details. llvm-svn: 325852
* [X86] Turn setne X, signedmax into setgt signedmax, X in LowerVSETCC to ↵Craig Topper2018-02-231-0/+15
| | | | | | | | | | avoid an invert We won't be able to fold the constant pool load, but its still better than materialing ones and xoring for the invert if we used PCMPEQ. This will fix another regression from D42948. llvm-svn: 325845
* [X86] Turn setne X, signedmin into setgt X, signedmin in LowerVSETCC to ↵Craig Topper2018-02-221-0/+11
| | | | | | | | | | avoid an invert This will fix one of the regressions from D42948. Differential Revision: https://reviews.llvm.org/D43531 llvm-svn: 325840
* [AArch64] Improve macro fusion test caseEvandro Menezes2018-02-221-3/+5
| | | | | | | Improve a vector in the test case for the fusion of address generation and loads or stores. Otherwise, NFC. llvm-svn: 325839
* Revert "[DebugInfo][FastISel] Fix dropping dbg.value()"Sander de Smalen2018-02-221-49/+0
| | | | | | | | | This patch reverts r325440 and r325438 because it triggers an assertion in SelectionDAGBuilder.cpp. Also having debug enabled may unintentionally affect code-gen. The patch is reverted until we find a better solution. llvm-svn: 325825
* [X86][AVX512] Add DQ+VLX scalar int<->fp tests cases for D43441Simon Pilgrim2018-02-222-14/+20
| | | | llvm-svn: 325804
* [mips] Generate memory dependencies for byVal argumentsStefan Maksimovic2018-02-222-2/+28
| | | | | | | | | | | | | | | | | | | | | There were no memory dependencies made between stores generated when lowering formal arguments and loads generated when call lowering byVal arguments which made the Post-RA scheduler place a load before a matching store. Make the fixed object stored to mutable so that the load instructions can have their memory dependencies added Set the frame object as isAliased which clears the underlying objects vector in ScheduleDAGInstrs::buildSchedGraph(). This results in addition of all stores as dependenies for loads. This problem appeared when passing a byVal parameter coupled with a fastcc function call. Differential Revision: https://reviews.llvm.org/D37515 llvm-svn: 325782
* [mips] Regenerate tests for D38128 (NFC)Simon Dardis2018-02-226-1468/+2787
| | | | llvm-svn: 325770
* Recommit: [ARM] f16 constant pool fixSjoerd Meijer2018-02-223-1/+113
| | | | | | | This recommits r325754; the modified and failing test case actually didn't need any modifications. llvm-svn: 325765
* [ARM] Fix issue with large xor constants.David Green2018-02-221-0/+29
| | | | | | | | | | Fixup to rL325573 for large xor constants. Thanks to Eli Friedman for the catch. Differential revision: https://reviews.llvm.org/D43549 llvm-svn: 325761
* Revert r325754 and r325755 (f16 literal pool) because buildbots were unhappy.Sjoerd Meijer2018-02-224-115/+3
| | | | llvm-svn: 325756
* Added a test that I forgot to svn add in my previous commit r325754.Sjoerd Meijer2018-02-221-0/+107
| | | | llvm-svn: 325755
* [ARM] f16 constant pool fixSjoerd Meijer2018-02-223-3/+8
| | | | | | | | | | | This is a follow up of r325012, that allowed half types in constant pools. Proper alignment was enforced when a big basic block was split up, but not when a CPE was placed before/after a block; the successor block had the wrong alignment. Differential Revision: https://reviews.llvm.org/D43580 llvm-svn: 325754
* [PowerPC] Do not produce invalid CTR loop with an FRemNemanja Ivanovic2018-02-221-0/+46
| | | | | | | | | | | An FRem instruction inside a loop should prevent the loop from being converted into a CTR loop since this is not an operation that is legal on any PPC subtarget. This will always be a call to a library function which means the loop will be invalid if this instruction is in the body. Fixes PR36292. llvm-svn: 325739
* [X86][MMX] Generlize MMX_MOVD64rr combines to accept v4i16/v8i8 build ↵Simon Pilgrim2018-02-211-350/+56
| | | | | | | | vectors as well as v2i32 Also handle both cases where the lower 32-bits of the MMX is undef or zero extended. llvm-svn: 325736
* [X86][MMX] Add MMX_MOVD64rr build vector tests showing undef elements in the ↵Simon Pilgrim2018-02-211-0/+204
| | | | | | lower half llvm-svn: 325729
* [X86][MMX] Run MMX bitcast test on 32 and 64-bit targetsSimon Pilgrim2018-02-211-19/+27
| | | | llvm-svn: 325707
* [X86][MMX] Regenerate MMX MASKMOV testSimon Pilgrim2018-02-211-4/+24
| | | | llvm-svn: 325698
* [Hexagon] Return true in enableMultipleCopyHints().Jonas Paulsson2018-02-213-5/+5
| | | | | | | | | | Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Krzysztof Parzyszek llvm-svn: 325697
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