[PowerPC] Disable shrink-wrapping when getting PC address through the LR

The instruction sequence used to get the address of the PC into a GPR requires
that we clobber the link register. Doing so without having first saved it in
the prologue leaves the function unable to return. Currently, this sequence is
emitted into the entry block. To ensure the prologue is inserted before this
sequence, disable shrink-wrapping.

This fixes PR33547.

Differential Revision: https://reviews.llvm.org/D43677

llvm-svn: 325972

1 files changed, 70 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/PowerPC/pr33547.ll b/llvm/test/CodeGen/PowerPC/pr33547.ll
new file mode 100644
index 00000000000..166b5c6327e
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/pr33547.ll
@@ -0,0 +1,70 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr8 -code-model=large < %s | FileCheck %s
+%struct.STATICS1 = type <{ [128 x i8] }>
+
+@.STATICS1 = internal global %struct.STATICS1 <{ [128 x i8] c"\09\00\00\00\03\00\00\00\05\00\00\00\04\00\00\00\0A\00\00\00\0A\00\00\00\0B\00\00\00\0A\08\AF/\B8\B6\87\04 \A1\07\00\08\9D\00\00\09\00\00\00\05\00\00\00\03\00\00\00\03\00\00\00\05\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00" }>, align 16
+@.C302_MAIN_ = internal constant i32 4
+
+; Function Attrs: noinline norecurse nounwind
+define void @main() {
+L.entry:
+  tail call void @testFunc(i64* bitcast (i8* getelementptr inbounds (%struct.STATICS1, %struct.STATICS1* @.STATICS1, i64 0, i32 0, i64 124) to i64*), i64* bitcast (i32* @.C302_MAIN_ to i64*))
+  ret void
+}
+
+; Function Attrs: noinline norecurse nounwind readonly
+define signext i32 @ifunc_(i64* nocapture readonly %i) {
+; CHECK-LABEL: ifunc_:
+; CHECK:       # %bb.0: # %L.entry
+; CHECK-NEXT:    lwa 3, 0(3)
+; CHECK-NEXT:    blr
+L.entry:
+  %0 = bitcast i64* %i to i32*
+  %1 = load i32, i32* %0, align 4
+  ret i32 %1
+}
+
+; Function Attrs: noinline norecurse nounwind
+define void @testFunc(i64* nocapture %r, i64* nocapture readonly %k) {
+; CHECK-LABEL: testFunc
+; CHECK: mflr 0
+; CHECK: std 0, 16(1)
+; CHECK: bl .[[BRANCHNEXT:[L0-9\$a-z]+]]
+; CHECK-NEXT: [[BRANCHNEXT]]
+L.entry:
+  %0 = bitcast i64* %k to i32*
+  %1 = load i32, i32* %0, align 4
+  switch i32 %1, label %L.LB3_307 [
+    i32 1, label %L.LB3_307.sink.split
+    i32 3, label %L.LB3_307.sink.split
+    i32 4, label %L.LB3_321.split
+    i32 5, label %L.LB3_307.sink.split
+    i32 6, label %infloop.preheader
+    i32 2, label %infloop11.preheader
+  ]
+
+infloop11.preheader:                              ; preds = %L.entry
+  br label %infloop11
+
+infloop.preheader:                                ; preds = %L.entry
+  br label %infloop
+
+L.LB3_321.split:                                  ; preds = %L.entry
+  br label %L.LB3_307.sink.split
+
+L.LB3_307.sink.split:                             ; preds = %L.LB3_321.split, %L.entry, %L.entry, %L.entry
+  %.sink = phi i32 [ 5, %L.LB3_321.split ], [ -3, %L.entry ], [ -3, %L.entry ], [ -3, %L.entry ]
+  %2 = bitcast i64* %r to i32*
+  store i32 %.sink, i32* %2, align 4
+  br label %L.LB3_307
+
+L.LB3_307:                                        ; preds = %L.LB3_307.sink.split, %L.entry
+  ret void
+
+infloop:                                          ; preds = %infloop.preheader, %infloop
+  br label %infloop
+
+infloop11:                                        ; preds = %infloop11.preheader, %infloop11
+  br label %infloop11
+}