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* Instruction fixes, added instructions, and AsmString changes in theSean Callanan2009-12-1815-197/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
* Re-enable 91381 with fixes.Evan Cheng2009-12-161-1/+0
| | | | llvm-svn: 91489
* Do better with physical reg operands (typically, from inline asm)Dale Johannesen2009-12-161-0/+49
| | | | | | | | | | | | | | | | | | in local register allocator. If a reg-reg copy has a phys reg input and a virt reg output, and this is the last use of the phys reg, assign the phys reg to the virt reg. If a reg-reg copy has a phys reg output and we need to reload its spilled input, reload it directly into the phys reg than passing it through another reg. Following 76208, there is sometimes no dependency between the def of a phys reg and its use; this creates a window where that phys reg can be used for spilling (this is true in linear scan also). This is bad and needs to be fixed a better way, although 76208 works too well in practice to be reverted. However, there should normally be no spilling within inline asm blocks. The patch here goes a long way towards making this actually be true. llvm-svn: 91485
* For fastcc on x86, let ECX be used as a return register after EAX and EDXKenneth Uildriks2009-12-151-0/+15
| | | | llvm-svn: 91410
* Disable 91381 for now. It's miscompiling ARMISelDAG2DAG.cpp.Evan Cheng2009-12-151-0/+1
| | | | llvm-svn: 91405
* Make 91378 more conservative.Evan Cheng2009-12-151-13/+0
| | | | | | | 1. Only perform (zext (shl (zext x), y)) -> (shl (zext x), y) when y is a constant. This makes sure it remove at least one zest. 2. If the shift is a left shift, make sure the original shift cannot shift out bits. llvm-svn: 91399
* Use sbb x, x to materialize carry bit in a GPR. The result is all one's or ↵Evan Cheng2009-12-151-0/+23
| | | | | | all zero's. llvm-svn: 91381
* Propagate zest through logical shift.Evan Cheng2009-12-152-0/+51
| | | | llvm-svn: 91378
* Fix integer cast code to handle vector types.Dan Gohman2009-12-141-0/+13
| | | | llvm-svn: 91362
* Disable r91104 for x86. It causes partial register stall which pessimize ↵Evan Cheng2009-12-121-1/+3
| | | | | | code in 32-bit. llvm-svn: 91223
* Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.Dan Gohman2009-12-111-0/+37
| | | | llvm-svn: 91158
* Change this to the correct PR number.Dan Gohman2009-12-111-1/+1
| | | | llvm-svn: 91148
* Fix the result type of SELECT nodes lowered from Select instructions withDan Gohman2009-12-111-0/+15
| | | | | | aggregate return values. This fixes PR5754. llvm-svn: 91145
* Honour setHasCalls() set from isel.Anton Korobeynikov2009-12-111-0/+63
| | | | | | | This is used in some weird cases like general dynamic TLS model. This fixes PR5723 llvm-svn: 91144
* Tests for 91103 and 91104.Evan Cheng2009-12-111-0/+93
| | | | llvm-svn: 91105
* It's not safe to coalesce a move where src and dst registers have different ↵Evan Cheng2009-12-101-0/+40
| | | | | | | | subregister indices. e.g.: %reg16404:1<def> = MOV8rr %reg16412:2<kill> llvm-svn: 91061
* Fix test.Evan Cheng2009-12-091-1/+1
| | | | llvm-svn: 90988
* Optimize splat of a scalar load into a shuffle of a vector load when it's ↵Evan Cheng2009-12-091-0/+43
| | | | | | | | | | | | legal. e.g. vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0> => vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1> iff ptr is 16-byte aligned (or can be made into 16-byte aligned). llvm-svn: 90984
* Use FileCheck and set nounwind on calls.David Greene2009-12-071-6/+7
| | | | llvm-svn: 90790
* Don't enable the post-RA scheduler on x86 except at -O3. In itsDan Gohman2009-12-078-8/+8
| | | | | | current form, it is too expensive in compile time. llvm-svn: 90781
* Temporarily revert r90502. It was causing the llvm-gcc bootstrap on PPC to fail.Bill Wendling2009-12-052-2/+2
| | | | llvm-svn: 90653
* Also attempt trivial coalescing for live intervals that end in a copy.Jakob Stoklund Olesen2009-12-042-2/+2
| | | | | | | | | | | | | The coalescer is supposed to clean these up, but when setting up parameters for a function call, there may be copies to physregs. If the defining instruction has been LICM'ed far away, the coalescer won't touch it. The register allocation hint does not always work - when the register allocator is backtracking, it clears the hints. This patch takes care of a few more cases that r90163 missed. llvm-svn: 90502
* Don't pull vector sext through both hands of a logical operation, since ↵Nate Begeman2009-12-031-0/+29
| | | | | | | | | doing so prevents the fusion of vector sext and setcc into vsetcc. Add a testcase for the above transformation. Fix a bogus use of APInt noticed while tracking this down. llvm-svn: 90423
* Remove unnecessary check.Bill Wendling2009-12-021-1/+0
| | | | llvm-svn: 90352
* Fix PR5391: support early clobber physical register def tied with a use (ewwww)Evan Cheng2009-12-011-0/+38
| | | | | | | | - A valno should be set HasRedefByEC if there is an early clobber def in the middle of its live ranges. It should not be set if the def of the valno is defined by an early clobber. - If a physical register def is tied to an use and it's an early clobber, it just means the HasRedefByEC is set since it's still one continuous live range. - Add a couple of missing checks for HasRedefByEC in the coalescer. In general, it should not coalesce a vr with a physical register if the physical register has a early clobber def somewhere. This is overly conservative but that's the price for using such a nasty inline asm "feature". llvm-svn: 90269
* Use CFG connectedness as a secondary sort key when deciding the order of ↵Jakob Stoklund Olesen2009-12-011-0/+1
| | | | | | | | | copy coalescing. This means that well connected blocks are copy coalesced before the less connected blocks. Connected blocks are more difficult to coalesce because intervals are more complicated, so handling them first gives a greater chance of success. llvm-svn: 90194
* New virtual registers created for spill intervals should inherit allocation ↵Jakob Stoklund Olesen2009-11-301-1/+1
| | | | | | | | | | | | | | | | | | | hints from the original register. This helps us avoid silly copies when rematting values that are copied to a physical register: leaq _.str44(%rip), %rcx movq %rcx, %rsi call _strcmp becomes: leaq _.str44(%rip), %rsi call _strcmp The coalescer will not touch the movq because that would tie down the physical register. llvm-svn: 90163
* Add test case for r90108Mon P Wang2009-11-301-0/+154
| | | | llvm-svn: 90109
* Test for 89905.Evan Cheng2009-11-261-0/+116
| | | | llvm-svn: 89906
* Turns out stuff gets allocated to different registers depending on the ↵Benjamin Kramer2009-11-221-1/+1
| | | | | | subtarget. llvm-svn: 89594
* Fix for bad FileCheck converts in revision 89584.Edward O'Callaghan2009-11-221-8/+12
| | | | llvm-svn: 89586
* Convert a few tests to FileCheck for PR5307.Edward O'Callaghan2009-11-225-12/+28
| | | | llvm-svn: 89584
* Enable hoisting load from constant memories.Evan Cheng2009-11-202-7/+1
| | | | llvm-svn: 89510
* Recommitting PALIGNR shift width fixes.Sean Callanan2009-11-201-3/+3
| | | | | | | Thanks to Daniel Dunbar for fixing clang intrinsics: http://llvm.org/viewvc/llvm-project?view=rev&revision=89499 llvm-svn: 89500
* Reverting PALIGNR fix until I figure out how thisSean Callanan2009-11-201-3/+3
| | | | | | broke the Clang testsuite. llvm-svn: 89495
* Fixed PALIGNR to take 8-bit rotations in all cases.Sean Callanan2009-11-201-3/+3
| | | | | | | Also fixed the corresponding testcase, and the PALIGNR intrinsic (tested for correctness with llvm-gcc). llvm-svn: 89491
* Fix fast-isel to avoid selecting the return instruction if aDan Gohman2009-11-201-0/+13
| | | | | | tail call has been encountered. llvm-svn: 89444
* Test from Dhrystone to make sure that we're not emitting an aligned load for aBill Wendling2009-11-191-0/+28
| | | | | | string that's aligned at 8-bytes instead of 16-bytes. llvm-svn: 89295
* Fix PR5300.Jakob Stoklund Olesen2009-11-181-0/+29
| | | | | | | | When TwoAddressInstructionPass deletes a dead instruction, make sure that all register kills are accounted for. The 2-addr register does not get special treatment. llvm-svn: 89246
* Fix inverted test and add testcase from failing self-host.Jakob Stoklund Olesen2009-11-181-0/+52
| | | | llvm-svn: 89167
* Remove fragile test.Jakob Stoklund Olesen2009-11-171-1/+0
| | | | llvm-svn: 89150
* Enable -split-phi-edges by default, except when -regalloc=local.Jakob Stoklund Olesen2009-11-172-1/+2
| | | | | | | The local register allocator doesn't like it when LiveVariables is run. We should also disable edge splitting under -O0, but that has to wait a bit. llvm-svn: 89125
* Revert 89021. It's miscompiling llvm-gcc driver driver at -O0.Evan Cheng2009-11-172-8/+2
| | | | llvm-svn: 89082
* Enable -split-phi-edges by defaultJakob Stoklund Olesen2009-11-172-2/+8
| | | | llvm-svn: 89021
* MOV64rm should be marked isReMaterializable.Evan Cheng2009-11-171-0/+42
| | | | llvm-svn: 89019
* Fix this test - there don't appear to be any actual Reload ReusesDan Gohman2009-11-161-1/+0
| | | | | | in this testcase. llvm-svn: 88998
* Revert r87049, which was the workaround for the regression triggeredDan Gohman2009-11-161-2/+2
| | | | | | | by the recent FixedStackPseudoSourceValue-related changes, now that the specific bug that affected it is fixed, in r88954. llvm-svn: 88997
* - Check memoperand alignment instead of checking stack alignment. Most load ↵Evan Cheng2009-11-161-0/+28
| | | | | | | | / store folding instructions are not referencing spill stack slots. - Mark MOVUPSrm re-materializable. llvm-svn: 88974
* Support spill comments.David Greene2009-11-161-0/+105
| | | | | | | | Have the asm printer emit a comment if an instruction is a spill or reload and have the spiller mark copies it introdues so the asm printer can also annotate those. llvm-svn: 88911
* Added getSubRegIndex(A,B) that returns subreg index of A to B. Use it to ↵Evan Cheng2009-11-141-0/+133
| | | | | | replace broken code in VirtRegRewriter. llvm-svn: 88753
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