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| author | Sean Callanan <scallanan@apple.com> | 2009-11-20 21:40:28 +0000 |
|---|---|---|
| committer | Sean Callanan <scallanan@apple.com> | 2009-11-20 21:40:28 +0000 |
| commit | fbed130173efffe38a6c40abc88b141023600be3 (patch) | |
| tree | 5c031c035f234ff72f1163d5faf541551d9d1267 /llvm/test/CodeGen/X86 | |
| parent | e064ad47419d98b2b35847a1a4b136770c8ffbde (diff) | |
| download | bcm5719-llvm-fbed130173efffe38a6c40abc88b141023600be3.tar.gz bcm5719-llvm-fbed130173efffe38a6c40abc88b141023600be3.zip | |
Fixed PALIGNR to take 8-bit rotations in all cases.
Also fixed the corresponding testcase, and the PALIGNR
intrinsic (tested for correctness with llvm-gcc).
llvm-svn: 89491
Diffstat (limited to 'llvm/test/CodeGen/X86')
| -rw-r--r-- | llvm/test/CodeGen/X86/palignr-2.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/X86/palignr-2.ll b/llvm/test/CodeGen/X86/palignr-2.ll index 2936641e95d..116d4c71814 100644 --- a/llvm/test/CodeGen/X86/palignr-2.ll +++ b/llvm/test/CodeGen/X86/palignr-2.ll @@ -9,12 +9,12 @@ define void @t1(<2 x i64> %a, <2 x i64> %b) nounwind ssp { entry: ; CHECK: t1: ; palignr $3, %xmm1, %xmm0 - %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %a, <2 x i64> %b, i32 24) nounwind readnone + %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %a, <2 x i64> %b, i8 24) nounwind readnone store <2 x i64> %0, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16 ret void } -declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i32) nounwind readnone +declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwind readnone define void @t2() nounwind ssp { entry: @@ -22,7 +22,7 @@ entry: ; palignr $4, _b, %xmm0 %0 = load <2 x i64>* bitcast ([4 x i32]* @b to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1] %1 = load <2 x i64>* bitcast ([4 x i32]* @a to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1] - %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i32 32) nounwind readnone + %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 32) nounwind readnone store <2 x i64> %2, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16 ret void } |
