summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/X86/vector-shift-shl-512.ll
Commit message (Expand)AuthorAgeFilesLines
* [X86][SSE] Add support for constant folding vector logical shift by immediatesSimon Pilgrim2017-01-241-3/+2
* [X86][AVX512BW] Vectorize v64i8 vector shiftsSimon Pilgrim2017-01-111-1032/+39
* [X86][AVX512DQ] Enable v16i16 vector shifts to use an extend+shift+truncate p...Simon Pilgrim2017-01-091-19/+8
* [X86][SSE] Standardized triples in vector shift testsSimon Pilgrim2017-01-061-154/+154
* [X86] Optimize vector shifts with variable but uniform shift amountsZvi Rackover2017-01-051-6/+3
* [X86][AVX512BW] Updated tests to demonstrate AVX512BW's inability to vectoriz...Simon Pilgrim2016-08-161-1/+1045
* [X86][SSE] Allow folding of store/zext with PEXTRW of 0'th elementSimon Pilgrim2016-07-211-4/+2
* [X86][AVX2] Fix v16i16 SHL lowering (PR27730)Simon Pilgrim2016-06-041-5/+5
* AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar ...Igor Breger2015-12-231-127/+157
* Make utils/update_llc_test_checks.py note that the assertions areJames Y Knight2015-11-231-0/+1
* [X86][AVX512] Added 512-bit vector shift tests.Simon Pilgrim2015-09-061-0/+262
OpenPOWER on IntegriCloud