summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/X86/vector-rotate-256.ll
Commit message (Expand)AuthorAgeFilesLines
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-19/+19
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-19/+19
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-90/+90
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-19/+19
* [SelectionDAG] Teach simplifyDemandedBits to handle shifts by constant splat ...Craig Topper2017-09-251-3/+3
* [AVX-512] Remove patterns that select vmovdqu8/16 for unmasked loads. Prefer ...Craig Topper2017-07-311-28/+14
* [X86] SET0 to use XMM registers where possible PR26018 PR32862Dinar Temirbulatov2017-07-271-2/+2
* [X86][AVX512] Add lowering of vXi32/vXi64 ISD::ROTL/ISD::ROTRSimon Pilgrim2017-07-171-53/+94
* [X86][AVX] Fix typo in vector rotate testsSimon Pilgrim2017-07-171-16/+10
* [DAGCombiner] Recognise vector rotations with non-splat constantsAndrew Zhogin2017-07-161-53/+26
* [X86][AVX] Regenerate tests with constant broadcast commentsSimon Pilgrim2017-07-151-4/+4
* [DAG] add splat vector support for 'and' in SimplifyDemandedBitsSanjay Patel2017-04-191-14/+3
* [X86][AVX512] Add vector rotate tests for AVX512 targetsSimon Pilgrim2017-02-101-0/+177
* [X86][SSE] Add support for constant folding vector logical shift by immediatesSimon Pilgrim2017-01-241-26/+22
* [X86][AVX2] Fix v16i16 SHL lowering (PR27730)Simon Pilgrim2016-06-041-6/+6
* [X86][SSE41] Avoid variable blend for constant v8i16 shiftsSimon Pilgrim2016-03-131-16/+8
* [X86][SSE] Fixed vector rotation test name typoSimon Pilgrim2016-02-241-5/+5
* Make utils/update_llc_test_checks.py note that the assertions areJames Y Knight2015-11-231-0/+1
* [X86][SSE] shift/rotate tests - remove unnecessary mcpu arguments and regener...Simon Pilgrim2015-10-251-4/+4
* [DAGCombiner] Generalize masking of constant rotates.Simon Pilgrim2015-10-241-23/+15
* [X86][XOP] Add support for lowering vector rotationsSimon Pilgrim2015-10-241-209/+105
* [X86][SSE] Add 256-bit vector bit rotation tests.Simon Pilgrim2015-10-201-0/+1200
OpenPOWER on IntegriCloud