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path: root/llvm/test/CodeGen/X86/vec_ctbits.ll
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* [x86] transform vector inc/dec to use -1 constant (PR33483)Sanjay Patel2017-06-261-18/+20
* [VectorLegalizer] Expansion of CTLZ using CTPOP when possibleSimon Pilgrim2016-11-081-25/+72
* [X86][SSE] Don't decide when to scalarize CTTZ/CTLZ for performance at loweri...Simon Pilgrim2016-08-041-21/+40
* [SelectionDAG] change getConstant() to use the input SDLoc when building spla...Sanjay Patel2016-02-111-5/+5
* Make utils/update_llc_test_checks.py note that the assertions areJames Y Knight2015-11-231-0/+1
* [X86][SSE] Refreshed vector bit count tests.Simon Pilgrim2015-07-261-26/+102
* llvm/test/CodeGen/X86/vec_ctbits.ll: Add explicit -mtriple=x86_64-unknown. It...NAKAMURA Takumi2014-09-121-1/+1
* Legalizer: Use the scalar bit width when promoting bit counting instrs onBenjamin Kramer2014-09-121-1/+50
* Manually upgrade the test suite to specify the flag to cttz and ctlz.Chandler Carruth2011-12-121-4/+4
* Eliminate more uses of llvm-as and llvm-dis.Dan Gohman2009-09-081-1/+1
* Add nounwind.Evan Cheng2008-05-291-3/+3
* Allow vector integer constants to be created withDan Gohman2007-12-121-0/+18
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