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path: root/llvm/test/CodeGen/X86/sat-add.ll
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* [X86][SSE] Generalized unsigned compares to support nonsplat constant vectors...Simon Pilgrim2019-01-261-4/+2
* [X86] Add nonsplat increment/decrement constant vector with min/max test (PR3...Simon Pilgrim2019-01-261-0/+27
* [x86] increment/decrement constant vector with min/max in vsetcc lowering (PR...Sanjay Patel2018-12-161-4/+2
* [TargetLowering] Add ISD::OR + ISD::XOR handling to SimplifyDemandedVectorEltsSimon Pilgrim2018-12-151-8/+6
* [X86] Stop promoting vector and/or/xor/andn to vXi64.Craig Topper2018-10-261-3/+4
* [X86] Move promotion of vector and/or/xor from legalization to DAG combineCraig Topper2018-10-151-35/+26
* [X86] When lowering unsigned v2i64 setcc without SSE42, flip the sign bits in...Craig Topper2018-10-091-41/+37
* [X86] Don't promote i16 compares to i32 if the immediate will fit in 8 bits.Craig Topper2018-10-051-2/+1
* [DAGCombiner] use UADDO to optimize saturated unsigned addSanjay Patel2018-09-241-16/+9
* [X86] Handle COPYs of physregs better (regalloc hints)Simon Pilgrim2018-09-191-10/+12
* [x86] test codegen for unsigned saturated add; NFCSanjay Patel2018-09-101-0/+949
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