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Project Ortega BCM5719 LLVM
Raptor Computing Systems
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llvm
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test
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CodeGen
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X86
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sat-add.ll
Commit message (
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Author
Age
Files
Lines
*
[X86][SSE] Generalized unsigned compares to support nonsplat constant vectors...
Simon Pilgrim
2019-01-26
1
-4
/
+2
*
[X86] Add nonsplat increment/decrement constant vector with min/max test (PR3...
Simon Pilgrim
2019-01-26
1
-0
/
+27
*
[x86] increment/decrement constant vector with min/max in vsetcc lowering (PR...
Sanjay Patel
2018-12-16
1
-4
/
+2
*
[TargetLowering] Add ISD::OR + ISD::XOR handling to SimplifyDemandedVectorElts
Simon Pilgrim
2018-12-15
1
-8
/
+6
*
[X86] Stop promoting vector and/or/xor/andn to vXi64.
Craig Topper
2018-10-26
1
-3
/
+4
*
[X86] Move promotion of vector and/or/xor from legalization to DAG combine
Craig Topper
2018-10-15
1
-35
/
+26
*
[X86] When lowering unsigned v2i64 setcc without SSE42, flip the sign bits in...
Craig Topper
2018-10-09
1
-41
/
+37
*
[X86] Don't promote i16 compares to i32 if the immediate will fit in 8 bits.
Craig Topper
2018-10-05
1
-2
/
+1
*
[DAGCombiner] use UADDO to optimize saturated unsigned add
Sanjay Patel
2018-09-24
1
-16
/
+9
*
[X86] Handle COPYs of physregs better (regalloc hints)
Simon Pilgrim
2018-09-19
1
-10
/
+12
*
[x86] test codegen for unsigned saturated add; NFC
Sanjay Patel
2018-09-10
1
-0
/
+949