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path: root/llvm/test/CodeGen/X86/horizontal-reduce-umax.ll
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* [DAGCombiner][x86] scalarize binop followed by extractelementSanjay Patel2019-01-031-110/+110
* [X86] Move promotion of vector and/or/xor from legalization to DAG combineCraig Topper2018-10-151-62/+48
* [X86] When lowering unsigned v2i64 setcc without SSE42, flip the sign bits in...Craig Topper2018-10-091-3/+3
* [SelectionDAG] enhance vector demanded elements to look at a vector select co...Sanjay Patel2018-09-091-24/+8
* Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"Geoff Berry2018-02-271-4/+4
* Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding"Quentin Colombet2018-02-171-4/+4
* [X86][SSE] Enable SMIN/SMAX/UMIN/UMAX custom lowering for all legal typesSimon Pilgrim2018-02-111-361/+252
* [MachineCopyPropagation] Extend pass to do COPY source forwardingGeoff Berry2018-02-011-4/+4
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-52/+52
* [X86] Use vpternlog to implement vector not under AVX512.Craig Topper2018-01-261-36/+74
* [X86][SSE] Use (V)PHMINPOSUW for vXi8 SMAX/SMIN/UMAX/UMIN horizontal reductio...Simon Pilgrim2017-12-191-163/+121
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-48/+48
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-98/+98
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-48/+48
* [X86][SSE] Use (V)PHMINPOSUW for vXi16 SMAX/SMIN/UMAX/UMIN horizontal reducti...Simon Pilgrim2017-11-231-127/+85
* [X86][SSE] Tests for integer min/max horizontal reductionsSimon Pilgrim2017-11-051-0/+2203
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