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path: root/llvm/test/CodeGen/X86/f16c-schedule.ll
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* [AsmPrinter] Remove hidden flag -print-schedule.Andrea Di Biagio2019-02-041-255/+0
* [X86] Fix VZEROUPPER scheduling info on SNB,HSW,BDW,SXL,SKX.Clement Courbet2018-11-091-5/+5
* AMD BdVer2 (Piledriver) Initial Scheduler modelRoman Lebedev2018-10-271-15/+15
* [NFC][X86] Baseline tests for AMD BdVer2 (Piledriver) Scheduler modelRoman Lebedev2018-10-271-0/+28
* [CodeGen] assume max/default throughput for unspecified instructionsSanjay Patel2018-06-051-9/+9
* [X86] Split off F16C WriteCvtPH2PS/WriteCvtPS2PH scheduler classesSimon Pilgrim2018-05-151-2/+2
* [X86][F16C] Add WriteCvtF2FSt scheduling classSimon Pilgrim2018-04-241-4/+4
* [X86][BtVer2] Fix VCVTPS2PHmr/VCVTPS2PHYmr latenciesSimon Pilgrim2018-04-241-2/+2
* [X86][SandyBridge] SBWriteResPair +5cy Memory FoldsSimon Pilgrim2018-04-061-10/+10
* [X86][Haswell]: Updating the scheduling information for the Haswell subtarget.Gadi Haber2017-12-081-8/+8
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-28/+28
* [X86][Broadwell] Added the instruction scheduling information for the Broadwe...Gadi Haber2017-10-241-7/+7
* Update f16c instruction scheduling on btver2.Andrew V. Tischenko2017-10-241-33/+33
* [X86][F16C] Regenerate F16C schedule testsSimon Pilgrim2017-10-231-28/+28
* [X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<...Gadi Haber2017-10-171-0/+28
* [X86][SKL] Updated scheduling information for the SkylakeClient targetGadi Haber2017-10-171-8/+8
* [X86][Skylake] Adding the scheduling information for the SkylakeClient targetGadi Haber2017-09-191-10/+10
* AMD family 17h (znver1) scheduler model update.Ashutosh Nema2017-08-311-13/+13
* [X86][Skylake] Fixing duplicated prefixes in the run command of Code Gen regr...Gadi Haber2017-08-301-1/+28
* [X86][Haswell] Updating HSW instruction scheduling informationGadi Haber2017-08-281-12/+12
* [X86] Added missing cpu to fix generic scheduling model testsSimon Pilgrim2017-08-011-0/+28
* This patch returns proper value to indicate the case when instruction through...Andrew V. Tischenko2017-07-261-3/+3
* AMD znver1 Initial Scheduler modelCraig Topper2017-07-191-13/+13
* [X86] Add F16C scheduling testsSimon Pilgrim2017-07-161-0/+144
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