summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/X86/compress_expand.ll
Commit message (Expand)AuthorAgeFilesLines
* [X86] Split expandload and compressstore testsSimon Pilgrim2019-04-061-416/+0
* [X86] Update masked expandload/compressstore test namesSimon Pilgrim2018-11-141-55/+53
* [X86] Turn X86ISD::VSEXT into X86ISD::VZEXT if the upper bits aren't demanded.Craig Topper2018-11-091-5/+5
* [X86] Use vpmovq2m/vpmovd2m for truncate to vXi1 when possible.Craig Topper2018-02-191-3/+3
* [SelectionDAG][X86] Fix incorrect offset generated for VMASKMOVAlexander Ivchenko2018-02-141-1/+1
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-11/+11
* [X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero...Craig Topper2018-01-271-20/+15
* [X86] Make v2i1 and v4i1 legal types without VLXCraig Topper2018-01-071-23/+15
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-11/+11
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-35/+35
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-11/+11
* [X86][AVX512] Improve lowering of AVX512 test intrinsicsUriel Korach2017-11-061-3/+1
* [X86] Add more patterns to use moves to zero the upper portions of a vector r...Craig Topper2017-09-031-8/+4
* [X86] Add patterns to turn an insert into lower subvector of a zero vector in...Craig Topper2017-09-031-2/+1
* [AVX512] Don't switch unmasked subvector insert/extract instructions when AVX...Craig Topper2017-08-171-1/+1
* [X86] SET0 to use XMM registers where possible PR26018 PR32862Dinar Temirbulatov2017-08-031-9/+9
* [X86] SET0 to use XMM registers where possible PR26018 PR32862Dinar Temirbulatov2017-07-271-1/+1
* Recommitting rL305465 after fixing bug in TableGen in rL306251 & rL306371Ayman Musa2017-06-271-6/+2
* Revert r305465: [X86][AVX512] Improve lowering of AVX512 compare intrinsics (...Simon Pilgrim2017-06-151-2/+6
* [X86][AVX512] Improve lowering of AVX512 compare intrinsics (remove redundant...Ayman Musa2017-06-151-6/+2
* [AVX-512] Fix accidental uses of AH/BH/CH/DH after copies to/from mask registersCraig Topper2017-03-281-15/+29
* [X86] Generate VZEROUPPER for Skylake-avx512.Amjad Aboud2017-03-031-16/+41
* [X86][AVX512] Add support for ASHR v2i64/v4i64 support without VLXSimon Pilgrim2017-02-201-2/+1
* This is a large patch for X86 AVX-512 of an optimization for reducing code si...Gadi Haber2016-12-281-3/+3
* [x86] use a single shufps when it can save instructionsSanjay Patel2016-12-151-4/+2
* Type legalization for compressstore and expandload intrinsics. Elena Demikhovsky2016-11-231-2/+161
* Expandload and Compressstore intrinsicsElena Demikhovsky2016-11-031-0/+247
OpenPOWER on IntegriCloud