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path: root/llvm/test/CodeGen/X86/combine-udiv.ll
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* [X86] Emit PACKUS directly from the v16i8 LowerMULH code instead of using a s...Craig Topper2018-11-301-2/+1
* [SelectionDAG][AArch64][X86] Move legalization of vector MULHS/MULHU from Leg...Craig Topper2018-11-291-29/+19
* [X86][SSE] Add SimplifyDemandedVectorElts support for PACKSS/PACKUS instructi...Simon Pilgrim2018-11-201-4/+3
* [X86] Add vector shift by immediate to SimplifyDemandedBitsForTargetNode.Craig Topper2018-11-041-26/+16
* [DAGCombiner] Fold 0 div/rem X to 0David Bolvansky2018-10-311-101/+7
* [DAGCombiner] Improve X div/rem Y fold if single bit element typeDavid Bolvansky2018-10-301-154/+5
* [DAGCombiner][NFC] Tests for X div/rem Y single bit foldDavid Bolvansky2018-09-291-0/+167
* [X86] Handle COPYs of physregs better (regalloc hints)Simon Pilgrim2018-09-191-1/+1
* [X86][SSE] Always enable ISD::SRL -> ISD::MULHU for v8i16Simon Pilgrim2018-09-161-55/+26
* [DAGCombiner] Add X / X -> 1 & X % X -> 0 foldsSimon Pilgrim2018-08-291-88/+15
* [X86][SSE] LowerMULH vXi8 - use SSE shifts directly.Simon Pilgrim2018-08-221-101/+35
* [X86][SSE] Add non-uniform udiv test that is mostly divide by 1.Simon Pilgrim2018-08-211-0/+178
* [X86] Add SSE2 and XOP udiv combine testsSimon Pilgrim2018-08-211-155/+515
* [X86] Add tests showing missing div/rem 0, X -> 0 combinesSimon Pilgrim2018-08-131-0/+67
* [TargetLowering] BuildUDIV - Add support for divide by one (PR38477)Simon Pilgrim2018-08-081-85/+19
* [X86][SSE] PR38477 test is more cleanly tested with udiv instead of uremSimon Pilgrim2018-08-081-110/+78
* [TargetLowering] BuildUDIV - Early out for divide by one (PR38477)Simon Pilgrim2018-08-081-0/+128
* [TargetLowering] Add support for non-uniform vectors to BuildUDIVSimon Pilgrim2018-08-071-290/+42
* [X86][SSE] Add more UDIV nonuniform-constant vector testsSimon Pilgrim2018-08-021-0/+238
* [X86] Add UDIV by uniform/non-uniform constant testsSimon Pilgrim2018-07-121-0/+126
* [DAGCombiner] Add special case fast paths for udiv x,1 and udiv x,-1Simon Pilgrim2018-07-101-35/+12
* [X86] Add srem/udiv/urem by constant testsSimon Pilgrim2018-07-101-0/+78
* [X86][SSE] Reduce instruction/register usages for v4i32 vector shifts (PR37441)Simon Pilgrim2018-05-161-45/+39
* [x86] consolidate and add tests for undef binop folds; NFCSanjay Patel2018-02-081-35/+0
* [X86] Add srem/udiv/urem by one combine testsSimon Pilgrim2018-01-041-0/+18
* [X86] Add scalar undef sdiv/srem/udiv/urem combine testsSimon Pilgrim2018-01-041-0/+17
* [X86] Add common CHECK prefix for tests without SSE/AVX codegenSimon Pilgrim2018-01-041-30/+15
* [X86] Show missed combine for X/X for SDIV/UDIV and X%X for SREM/UREMSimon Pilgrim2018-01-041-0/+66
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-18/+18
* [X86][AVX] Regenerate combine tests with constant broadcast commentsSimon Pilgrim2017-07-161-1/+1
* [SelectionDAG] Recognise splat vector isKnownToBeAPowerOfTwo one/sign bit shi...Simon Pilgrim2017-04-251-0/+47
* [DAGCombiner] Try to use SelectionDAG::isKnownToBeAPowerOfTwo instead of just...Simon Pilgrim2016-12-141-93/+54
* [X86][SSE] Add AVX1 tests to sdiv/udiv srem/urem combine testsSimon Pilgrim2016-12-141-33/+80
* [DAGCombiner] Add splatted vector support to (udiv x, (shl pow2, y)) -> x >>u...Simon Pilgrim2016-10-181-47/+19
* [X86][SSE] Added vector udiv combine testsSimon Pilgrim2016-09-171-0/+199
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