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path: root/llvm/test/CodeGen/X86/combine-pmuldq.ll
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* [X86][SSE] combinePMULDQ - pmuldq(x, 0) -> zero vector (PR43159)Simon Pilgrim2019-08-291-0/+115
* [TargetLowering] SimplifyDemandedBits ZERO_EXTEND_VECTOR_INREG -> ANY_EXTEND_...Simon Pilgrim2019-06-251-10/+7
* Revert r363802, r363850, and r363856 "[TargetLowering] SimplifyDemandedBits..."Craig Topper2019-06-251-7/+10
* [TargetLowering] SimplifyDemandedBits ZERO_EXTEND_VECTOR_INREG -> ANY_EXTEND_...Simon Pilgrim2019-06-191-10/+7
* Revert rL356864 : [X86][SSE41] Start shuffle combining from ZERO_EXTEND_VECTO...Simon Pilgrim2019-03-271-8/+8
* [X86][SSE41] Start shuffle combining from ZERO_EXTEND_VECTOR_INREG (PR40685)Simon Pilgrim2019-03-241-8/+8
* [X86] Avoid icmp undef in reduced testsSimon Pilgrim2019-03-131-4/+4
* [X86][SSE] Add SimplifyDemandedBitsForTargetNode PMULDQ/PMULUDQ handlingSimon Pilgrim2018-10-241-26/+4
* [X86][SSE] Revert rL343922 combinePMULDQ AddToWorklist (PR39398)Simon Pilgrim2018-10-231-4/+71
* [X86] combinePMULDQ - add op back to worklist if SimplifyDemandedBits succeed...Simon Pilgrim2018-10-061-26/+4
* [SelectionDAG] Add SimplifyDemandedBits to SimplifyDemandedVectorElts simplif...Simon Pilgrim2018-10-061-17/+1
* [X86] Combine vXi64 multiplies to MULDQ/MULUDQ during DAG combine instead of ...Craig Topper2018-04-071-20/+2
* [X86] Reimplement r321437 using custom lowering instead of as a DAG combine.Craig Topper2017-12-271-2/+2
* [X86] Fix vmul combine for AVX1 targets.Benjamin Kramer2017-12-271-0/+44
* [X86] Add a DAG combines to turn vXi64 muls into VPMULDQ/VPMULUDQ if the uppe...Craig Topper2017-12-251-52/+16
* [X86] Add avx512vl and avx512dq command lines to combine-pmuldq.ll to demonst...Craig Topper2017-12-251-31/+101
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-8/+8
* [X86] SET0 to use XMM registers where possible PR26018 PR32862Dinar Temirbulatov2017-07-271-1/+1
* [X86][SSE] Add combine tests for PMULDQ/PMULUDQSimon Pilgrim2017-06-261-0/+110
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