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Project Ortega BCM5719 LLVM
Raptor Computing Systems
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llvm
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test
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CodeGen
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X86
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combine-and.ll
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Author
Age
Files
Lines
*
[X86][SSE] Combine (VSRLI (VSRAI X, Y), (NumSignBits-1)) -> (VSRLI X, (NumSig...
Simon Pilgrim
2017-03-25
1
-1
/
+0
*
[X86][SSE] Added ComputeNumSignBitsForTargetNode support for (V)PSRAI
Simon Pilgrim
2017-03-25
1
-2
/
+2
*
[X86][SSE] Add ashr + mask test cases.
Simon Pilgrim
2017-03-24
1
-0
/
+26
*
[DAG] x & x --> x
Sanjay Patel
2016-10-30
1
-2
/
+0
*
[x86] add tests for basic logic op folds
Sanjay Patel
2016-10-30
1
-0
/
+19
*
[SelectionDAG] Add BUILD_VECTOR support to computeKnownBits and SimplifyDeman...
Simon Pilgrim
2016-09-08
1
-8
/
+2
*
[DAGCombiner] Enable AND combines of splatted constant vectors
Simon Pilgrim
2016-09-08
1
-4
/
+2
*
[X86][SSE] Added and+or+zext combine tests for known bits of vectors
Simon Pilgrim
2016-09-07
1
-0
/
+32
*
[X86][SSE] Added and+or combine tests currently failing with vectors
Simon Pilgrim
2016-09-07
1
-1
/
+28
*
Make utils/update_llc_test_checks.py note that the assertions are
James Y Knight
2015-11-23
1
-0
/
+1
*
[x86] Port this test to use utils/update_llc_test_checks.py.
Chandler Carruth
2015-02-04
1
-67
/
+81
*
[X86][SSE] Keep 4i32 vector insertions in integer domain on SSE4.1 targets
Simon Pilgrim
2014-12-02
1
-1
/
+1
*
[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks.
Andrea Di Biagio
2014-11-05
1
-0
/
+164