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path: root/llvm/test/CodeGen/X86/combine-and.ll
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* [X86][SSE] Combine (VSRLI (VSRAI X, Y), (NumSignBits-1)) -> (VSRLI X, (NumSig...Simon Pilgrim2017-03-251-1/+0
* [X86][SSE] Added ComputeNumSignBitsForTargetNode support for (V)PSRAISimon Pilgrim2017-03-251-2/+2
* [X86][SSE] Add ashr + mask test cases.Simon Pilgrim2017-03-241-0/+26
* [DAG] x & x --> xSanjay Patel2016-10-301-2/+0
* [x86] add tests for basic logic op foldsSanjay Patel2016-10-301-0/+19
* [SelectionDAG] Add BUILD_VECTOR support to computeKnownBits and SimplifyDeman...Simon Pilgrim2016-09-081-8/+2
* [DAGCombiner] Enable AND combines of splatted constant vectorsSimon Pilgrim2016-09-081-4/+2
* [X86][SSE] Added and+or+zext combine tests for known bits of vectorsSimon Pilgrim2016-09-071-0/+32
* [X86][SSE] Added and+or combine tests currently failing with vectorsSimon Pilgrim2016-09-071-1/+28
* Make utils/update_llc_test_checks.py note that the assertions areJames Y Knight2015-11-231-0/+1
* [x86] Port this test to use utils/update_llc_test_checks.py.Chandler Carruth2015-02-041-67/+81
* [X86][SSE] Keep 4i32 vector insertions in integer domain on SSE4.1 targetsSimon Pilgrim2014-12-021-1/+1
* [X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks.Andrea Di Biagio2014-11-051-0/+164
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