summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/X86/bmi-schedule.ll
Commit message (Expand)AuthorAgeFilesLines
* AMD BdVer2 (Piledriver) Initial Scheduler modelRoman Lebedev2018-10-271-47/+47
* [NFC][X86] Baseline tests for AMD BdVer2 (Piledriver) Scheduler modelRoman Lebedev2018-10-271-0/+93
* [X86][BMI1] Fix BLSI/BLSMSK/BLSR BMI1 scheduling on btver2Simon Pilgrim2018-09-141-12/+12
* [X86][BMI1] Remove test for non-existent andn i16 instructionSimon Pilgrim2018-06-021-62/+0
* [X86][SandyBridge] SBWriteResPair +5cy Memory FoldsSimon Pilgrim2018-04-061-10/+10
* [X86] Correct the placement of ReadAfterLd in BEXTR and BZHI. Add dedicated S...Craig Topper2018-03-291-4/+4
* Fix newlines. NFCI.Simon Pilgrim2018-03-261-732/+732
* [X86] Add WriteBitScan/WriteLZCNT/WriteTZCNT/WritePOPCNT scheduler classes (P...Simon Pilgrim2018-03-261-732/+732
* [X86][Btver2] Add correct lzcnt/tzcnt/popcnt schedule costsSimon Pilgrim2018-03-161-6/+6
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-12/+12
* [X86][Haswell]: Updating the scheduling information for the Haswell subtarget.Gadi Haber2017-12-081-28/+28
* [X86] Tag BMI/BMI2/TBM instructions scheduler classesSimon Pilgrim2017-12-071-32/+32
* [X86] Tag LZCNT/TZCNT instructions scheduler classesSimon Pilgrim2017-12-071-12/+12
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-12/+12
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-84/+84
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-12/+12
* [X86][Broadwell] Added the instruction scheduling information for the Broadwe...Gadi Haber2017-10-241-28/+28
* [X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<...Gadi Haber2017-10-171-0/+102
* [X86][SKL] Updated scheduling information for the SkylakeClient targetGadi Haber2017-10-171-28/+28
* [X86][SKYLAKE] Update regression test to differentiate between HASWELL and SK...Gadi Haber2017-10-101-1/+102
* AMD family 17h (znver1) scheduler model update.Ashutosh Nema2017-08-311-36/+36
* [X86][Haswell] Updating HSW instruction scheduling informationGadi Haber2017-08-281-28/+28
* [X86][SandyBridge] Additional updates to the SNB instructions scheduling info...Gadi Haber2017-08-131-1/+1
* [X86] Added missing cpu to fix generic scheduling model testsSimon Pilgrim2017-08-011-36/+36
* This patch returns proper value to indicate the case when instruction through...Andrew V. Tischenko2017-07-261-44/+44
* AMD znver1 Initial Scheduler modelCraig Topper2017-07-191-1/+102
* [X86] Add BMI1 scheduling testsSimon Pilgrim2017-07-161-0/+428
OpenPOWER on IntegriCloud