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path: root/llvm/test/CodeGen/X86/bitcast-setcc-512.ll
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* [X86][AVX] truncateVectorWithPACK - avoid bitcasted shufflesSimon Pilgrim2019-06-261-3/+0
* Recommit r358887 "[TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits ...Craig Topper2019-05-131-5/+3
* Revert r359392 and r358887Craig Topper2019-05-061-3/+5
* [TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits bitcast handlingSimon Pilgrim2019-04-221-5/+3
* [X86][SSE] SimplifyDemandedBitsForTargetNode - Add initial PACKSS supportSimon Pilgrim2019-04-071-37/+8
* [X86][SSE] SimplifyDemandedBitsForTargetNode - PCMPGT(0,X) sign maskSimon Pilgrim2019-02-041-7/+2
* [X86] Use two pmovmskbs in combineBitcastvxi1 for (i64 (bitcast (v64i1 (trunc...Craig Topper2019-01-051-19/+3
* [X86] Prevent DAG combine from folding a bitcast from vXi1 to iX with a store...Craig Topper2018-11-271-1311/+86
* [X86] Add a bunch of test cases for storing a scalar bitcasted from a vXi1 type.Craig Topper2018-11-271-0/+1518
* [X86] Add a custom legalization for (i16 (bitcast v16i1)) and (i32 (bitcast v...Craig Topper2018-02-261-758/+16
* [X86][SSE] truncateVectorWithPACK - Use src type instead of dst to select bet...Simon Pilgrim2018-02-141-2/+2
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-20/+20
* [X86] Legalize v32i1 without BWI via splitting to v16i1 rather than the defau...Craig Topper2018-01-231-34/+19
* [SelectionDAG] Fix codegen of vector stores with non byte-sized elements.Jonas Paulsson2018-01-201-576/+728
* [X86] Use ISD::TRUNCATE instead of X86ISD::VTRUNC when input and output types...Craig Topper2018-01-141-4/+0
* [X86] In LowerTruncateVecI1, don't add SHL if the input is known to be all si...Craig Topper2018-01-011-6/+0
* [SelectionDAG][X86] Improve legalization of v32i1 CONCAT_VECTORS of v16i1 for...Craig Topper2017-12-141-130/+2
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-20/+20
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-30/+30
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-20/+20
* Revert "Correct dwarf unwind information in function epilogue for X86"Reid Kleckner2017-11-081-4/+0
* Reland "Correct dwarf unwind information in function epilogue for X86"Petar Jovanovic2017-11-071-0/+4
* Revert "Correct dwarf unwind information in function epilogue for X86"Petar Jovanovic2017-11-011-4/+0
* Correct dwarf unwind information in function epilogue for X86Petar Jovanovic2017-11-011-0/+4
* [X86] truncateVectorCompareWithPACKSS - use PACKSSDW/PACKSSWB instead of just...Simon Pilgrim2017-10-241-20/+20
* [X86][SSE] combineBitcastvxi1 - use PACKSSWB directly to pack v8i16 to v16i8Simon Pilgrim2017-10-231-2/+2
* [MC] Suppress .Lcfi labels when emitting textual assemblyReid Kleckner2017-10-101-12/+0
* [X86][AVX] Improve (i8 bitcast (v8i1 x)) handling for v8i64/v8f64 512-bit vec...Simon Pilgrim2017-10-041-14/+6
* [X86][SSE] Add pre-AVX2 support for (i32 bitcast(v32i1)) -> 2xMOVMSKSimon Pilgrim2017-07-211-219/+22
* [X86][SSE] Fix file check prefix warning breaking buildbotsSimon Pilgrim2017-07-121-2/+2
* [X86][SSE] Add 512-bit (iX bitcast(vXi1)) test casesSimon Pilgrim2017-07-121-0/+1377
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