summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/X86/bitcast-setcc-256.ll
Commit message (Expand)AuthorAgeFilesLines
* Recommit r358887 "[TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits ...Craig Topper2019-05-131-16/+0
* Revert r359392 and r358887Craig Topper2019-05-061-0/+16
* [TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits bitcast handlingSimon Pilgrim2019-04-221-16/+0
* [X86][SSE] SimplifyDemandedBitsForTargetNode - Add initial PACKSS supportSimon Pilgrim2019-04-071-16/+5
* [X86][SSE] SimplifyDemandedBitsForTargetNode - PCMPGT(0,X) sign maskSimon Pilgrim2019-02-041-4/+1
* [X86] Allow combinevxi1Bitcast to use pmovmskb on avx512 targets if the input...Craig Topper2019-01-051-9/+1
* [TargetLowering] Add ISD::OR + ISD::XOR handling to SimplifyDemandedVectorEltsSimon Pilgrim2018-12-151-32/+25
* [X86] Prevent DAG combine from folding a bitcast from vXi1 to iX with a store...Craig Topper2018-11-271-622/+33
* [X86] Add a bunch of test cases for storing a scalar bitcasted from a vXi1 type.Craig Topper2018-11-271-0/+803
* [X86] When lowering unsigned v2i64 setcc without SSE42, flip the sign bits in...Craig Topper2018-10-091-1/+1
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-23/+23
* [X86] Legalize v32i1 without BWI via splitting to v16i1 rather than the defau...Craig Topper2018-01-231-14/+6
* [X86] In LowerTruncateVecI1, don't add SHL if the input is known to be all si...Craig Topper2018-01-011-3/+0
* [X86] Add a DAG combine to widen (i4 (bitcast (v4i1))) before type legalizati...Craig Topper2017-12-311-8/+4
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-19/+19
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-28/+28
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-19/+19
* Revert "Correct dwarf unwind information in function epilogue for X86"Reid Kleckner2017-11-081-1/+0
* Reland "Correct dwarf unwind information in function epilogue for X86"Petar Jovanovic2017-11-071-0/+1
* Revert "Correct dwarf unwind information in function epilogue for X86"Petar Jovanovic2017-11-011-1/+0
* Correct dwarf unwind information in function epilogue for X86Petar Jovanovic2017-11-011-0/+1
* [X86][AVX512] Split AVX512F and AVX512BW bool-vector bitcast testsSimon Pilgrim2017-10-311-44/+115
* [X86] truncateVectorCompareWithPACKSS - use PACKSSDW/PACKSSWB instead of just...Simon Pilgrim2017-10-241-4/+4
* [X86][SSE] combineBitcastvxi1 - use PACKSSWB directly to pack v8i16 to v16i8Simon Pilgrim2017-10-231-40/+18
* [X86][AVX] Improve (i4 bitcast (v4i1 x)) handling for 256-bit vector compare ...Simon Pilgrim2017-09-271-19/+9
* [X86][AVX] Improve (i8 bitcast (v8i1 x)) handling for 256-bit vector compare ...Simon Pilgrim2017-09-181-21/+9
* [X86][SSE] Add pre-AVX2 support for (i32 bitcast(v32i1)) -> 2xMOVMSKSimon Pilgrim2017-07-211-214/+11
* [X86][SSE] Dropped -mcpu from bitcast+setcc testsSimon Pilgrim2017-07-061-22/+397
* [X86] Match bitcast of vxi1 to pmovmskZvi Rackover2017-06-011-243/+11
* [X86] Add explicit triple to test invocationZvi Rackover2017-05-181-20/+20
* [X86] Adding tests for scalar bitcasts from vsetcc. NFC.Zvi Rackover2017-05-181-0/+363
OpenPOWER on IntegriCloud