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path: root/llvm/test/CodeGen/X86/bitcast-setcc-128.ll
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* [X86][SSE] SimplifyDemandedBitsForTargetNode - Add initial PACKSS supportSimon Pilgrim2019-04-071-6/+2
* [X86][SSE] SimplifyDemandedBitsForTargetNode - PCMPGT(0,X) sign maskSimon Pilgrim2019-02-041-3/+0
* [X86] Allow combinevxi1Bitcast to use pmovmskb on avx512 targets if the input...Craig Topper2019-01-051-4/+1
* [TargetLowering] Add ISD::OR + ISD::XOR handling to SimplifyDemandedVectorEltsSimon Pilgrim2018-12-151-26/+18
* [X86] Prevent DAG combine from folding a bitcast from vXi1 to iX with a store...Craig Topper2018-11-271-187/+12
* [X86] Add a bunch of test cases for storing a scalar bitcasted from a vXi1 type.Craig Topper2018-11-271-0/+319
* [X86] Stop promoting vector and/or/xor/andn to vXi64.Craig Topper2018-10-261-1/+0
* [X86] When lowering unsigned v2i64 setcc without SSE42, flip the sign bits in...Craig Topper2018-10-091-4/+4
* [X86][SSE] Combine (some) target shuffles with multiple usesSimon Pilgrim2018-08-091-12/+8
* [X86] Post process the DAG after isel to remove vector moves that were added ...Craig Topper2018-03-161-1/+0
* [X86] Add constant folding to combineMOVMSK.Craig Topper2018-02-261-22/+65
* [X86] Add a custom legalization for (i16 (bitcast v16i1)) and (i32 (bitcast v...Craig Topper2018-02-261-145/+32
* [X86] Remove VT.isSimple() check from detectAVGPattern.Craig Topper2018-02-261-0/+176
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-51/+51
* [X86] In LowerTruncateVecI1, don't add SHL if the input is known to be all si...Craig Topper2018-01-011-3/+0
* [X86] Add a DAG combine to widen (i4 (bitcast (v4i1))) before type legalizati...Craig Topper2017-12-311-36/+18
* [X86] When lowering truncates to vXi1, don't sign extend i16/i8 types to 512-...Craig Topper2017-12-211-6/+6
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-33/+33
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-51/+51
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-33/+33
* [X86][AVX512] Split AVX512F and AVX512BW bool-vector bitcast testsSimon Pilgrim2017-10-311-106/+236
* [X86][SSE] Add support for lowering shuffles to PACKSS/PACKUSSimon Pilgrim2017-10-031-42/+20
* [X86][SSE] Dropped -mcpu from bitcast+setcc testsSimon Pilgrim2017-07-061-78/+78
* [X86] Match bitcast of vxi1 to pmovmskZvi Rackover2017-06-011-452/+185
* [X86] Add (ix bitcast(vsetcc)) test cases with illegal types. NFC.Zvi Rackover2017-05-221-324/+594
* [X86] Add explicit triple to test invocationZvi Rackover2017-05-181-30/+30
* [X86] Adding tests for scalar bitcasts from vsetcc. NFC.Zvi Rackover2017-05-181-0/+553
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