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path: root/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
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* [X86] Add a VBROADCAST_LOAD ISD opcode representing a scalar load broadcasted...Craig Topper2019-10-011-14/+14
* [X86] Pass v32i16/v64i8 in zmm registers on KNL target.Craig Topper2019-08-301-11/+12
* [X86][AVX1] Combine concat_vectors(pshufd(x,c),pshufd(y,c)) -> vpermilps(conc...Simon Pilgrim2019-07-041-6/+3
* [X86][SSE] Fold scalar_to_vector(i64 anyext(x)) -> bitcast(scalar_to_vector(i...Simon Pilgrim2019-03-151-14/+7
* [X86] Stop promoting vector and/or/xor/andn to vXi64.Craig Topper2018-10-261-1/+1
* [X86][AVX] Enable lowerVectorShuffleAsLanePermuteAndPermute v16i16/v32i8 unar...Simon Pilgrim2018-10-211-76/+28
* [X86] Add 128 MOVDDUP to the constant pool printing in X86AsmPrinter::EmitIns...Craig Topper2018-10-151-1/+2
* [X86] Legalize zero extends from vXi1 to vXi16/vXi32/vXi64 using a sign exten...Craig Topper2018-02-101-28/+45
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-14/+14
* [X86] Legalize v32i1 without BWI via splitting to v16i1 rather than the defau...Craig Topper2018-01-231-51/+23
* X86 Tests: Update more isel tests with FastVariableShuffle featureZvi Rackover2018-01-091-42/+79
* [X86] Make v2i1 and v4i1 legal types without VLXCraig Topper2018-01-071-3/+0
* [X86] Add a DAG combine to fix (v4i1 (bitcast (i4))) before type legalization...Craig Topper2017-12-311-3/+0
* [X86] Prevent combining (v8i1 (bitconvert (i8 load)))->(v8i1 load) if we don'...Craig Topper2017-12-311-18/+6
* [X86][SSE] Match PSHUFLW/PSHUFHW + PSHUFD vXi16 shuffle patterns (PR34686)Simon Pilgrim2017-12-291-16/+16
* [X86] When lowering extending loads from v2i1/v4i1, if we have VLX, use a nar...Craig Topper2017-12-281-8/+3
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-17/+17
* [X86] Use vector widening to support zero extend from i1 when the dest type i...Craig Topper2017-12-051-7/+7
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-61/+61
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-15/+15
* [X86] Make zero extend from v16i1/v8i1 to v16i8/v8i16/v16i16 not scalarize un...Craig Topper2017-11-281-650/+34
* [X86] Add command line without AVX512BW/AVX512VL to bitcast-int-to-vector-boo...Craig Topper2017-11-281-201/+845
* Revert "Correct dwarf unwind information in function epilogue for X86"Reid Kleckner2017-11-081-6/+0
* Reland "Correct dwarf unwind information in function epilogue for X86"Petar Jovanovic2017-11-071-0/+6
* Revert "Correct dwarf unwind information in function epilogue for X86"Petar Jovanovic2017-11-011-6/+0
* Correct dwarf unwind information in function epilogue for X86Petar Jovanovic2017-11-011-0/+6
* [MC] Suppress .Lcfi labels when emitting textual assemblyReid Kleckner2017-10-101-12/+0
* [X86][SSE] Add support for extending bool vectors bitcasted from scalarsSimon Pilgrim2017-09-241-2831/+512
* Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding"Geoff Berry2017-08-171-4/+4
* [MachineCopyPropagation] Extend pass to do COPY source forwardingGeoff Berry2017-08-161-4/+4
* [X86][SSE] Tests for bitcasting iX integers to vXi1 boolean vectorsSimon Pilgrim2017-07-061-0/+3279
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