summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/X86/bitcast-and-setcc-128.ll
Commit message (Expand)AuthorAgeFilesLines
* [X86][SSE] lowerV16I8Shuffle - tryToWidenViaDuplication - undef unpack argsSimon Pilgrim2019-10-191-5/+5
* Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization...Craig Topper2019-08-071-486/+167
* Revert "[X86] Enable -x86-experimental-vector-widening-legalization by default."Mitch Phillips2019-08-061-167/+486
* [X86] Enable -x86-experimental-vector-widening-legalization by default.Craig Topper2019-08-051-486/+167
* [X86] Allow combinevxi1Bitcast to use pmovmskb on avx512 targets if the input...Craig Topper2019-01-051-4/+1
* [DAGCombiner] allow hoisting vector bitwise logic ahead of truncatesSanjay Patel2018-12-161-11/+8
* [TargetLowering] Add ISD::OR + ISD::XOR handling to SimplifyDemandedVectorEltsSimon Pilgrim2018-12-151-61/+45
* [X86] When lowering unsigned v2i64 setcc without SSE42, flip the sign bits in...Craig Topper2018-10-091-4/+4
* [X86][SSE] Combine (some) target shuffles with multiple usesSimon Pilgrim2018-08-091-24/+16
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-51/+51
* [X86] In LowerTruncateVecI1, don't add SHL if the input is known to be all si...Craig Topper2018-01-011-6/+0
* [X86] Add a DAG combine to widen (i4 (bitcast (v4i1))) before type legalizati...Craig Topper2017-12-311-36/+18
* [X86] When lowering truncates to vXi1, don't sign extend i16/i8 types to 512-...Craig Topper2017-12-211-12/+12
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-33/+33
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-51/+51
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-33/+33
* [X86][AVX512] Regenerate tests to remove retl/retq regexSimon Pilgrim2017-10-311-51/+51
* [X86][AVX512] Split AVX512F and AVX512BW bool-vector bitcast testsSimon Pilgrim2017-10-311-142/+317
* [X86][SSE] combineBitcastvxi1 - use PACKSSWB directly to pack v8i16 to v16i8Simon Pilgrim2017-10-231-58/+28
* [X86][SSE] Regenerate bitcast-and-setcc testsSimon Pilgrim2017-10-231-41/+41
* [X86][SSE] Dropped -mcpu from bitcast+setcc mask testsSimon Pilgrim2017-07-051-78/+78
* [X86] Match bitcast of vxi1 to pmovmskZvi Rackover2017-06-011-431/+108
* Add LiveRangeShrink pass to shrink live range within BB.Dehao Chen2017-05-311-68/+68
* [X86] Add tests for (ix bitcast (vxi1 and ...)). NFC.Zvi Rackover2017-05-291-0/+1155
OpenPOWER on IntegriCloud