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path: root/llvm/test/CodeGen/X86/avx512-memfold.ll
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* [X86] In getScalarMaskingNode, replace scalar_to_vector with a bitcast to v8i...Craig Topper2018-11-211-1/+1
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-1/+1
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-1/+1
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-5/+5
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-1/+1
* [X86] When selecting sse_load_f32/f64 pattern, make sure there's only one use...Craig Topper2017-08-211-2/+3
* [AVX512] Add a test to check what happens when a load is referenced by two di...Craig Topper2017-08-201-0/+21
* [X86][AVX512] Make i1 illegal in the CodeGenGuy Blank2017-05-191-5/+0
* [AVX-512] Use sse_load_f32/f64 in place of scalar_to_vector and scalar load i...Craig Topper2017-02-211-8/+4
* [AVX-512] Add test cases showing failure to fold zero extending scalar loads ...Craig Topper2017-02-211-0/+77
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