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path: root/llvm/test/CodeGen/X86/avx512-insert-extract.ll
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* [X86] Optimization of inserting vxi1 sub vector into vXi1 vectorWang, Pengfei2020-01-031-55/+36
* [X86] Rewrite to the vXi1 subvector insertion code to not rely on the value o...Craig Topper2019-10-021-33/+57
* [X86] Add VMOVSSZrrk/VMOVSDZrrk/VMOVSSZrrkz/VMOVSDZrrkz to getUndefRegClearance.Craig Topper2019-09-261-2/+2
* [X86] Pass v32i16/v64i8 in zmm registers on KNL target.Craig Topper2019-08-301-14/+21
* [X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.Craig Topper2019-07-061-2/+2
* [X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQSimon Pilgrim2019-06-261-8/+10
* Teach the DAGCombine to fold this pattern(c1 and c2 is constant).QingShan Zhang2019-06-261-20/+16
* [TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ...Simon Pilgrim2019-06-251-22/+22
* [X86] Custom lower CONCAT_VECTORS of v2i1Benjamin Kramer2019-05-281-0/+104
* [X86] Explcitly disable VEXTRACT instruction matching for an immediate of 0. ...Craig Topper2019-05-221-2/+2
* [SelectionDAG] Add icmp UNDEF handling to SelectionDAG::FoldSetCCSimon Pilgrim2019-03-251-61/+60
* [X86] Change vXi1 extract_vector_elt lowering to be legal if the index is 0. ...Craig Topper2019-01-111-2/+2
* [x86] allow vector load narrowing with multi-use valuesSanjay Patel2018-11-101-70/+50
* [X86] Turn X86ISD::VSEXT into X86ISD::VZEXT if the upper bits aren't demanded.Craig Topper2018-11-091-22/+22
* [DAGCombiner] narrow vector binops when extraction is cheapSanjay Patel2018-10-301-4/+4
* [X86] Move promotion of vector and/or/xor from legalization to DAG combineCraig Topper2018-10-151-3/+0
* [X86] Handle COPYs of physregs better (regalloc hints)Simon Pilgrim2018-09-191-16/+16
* [X86] Prefer blendi over movss/sd when avx512 is enabled unless optimizing fo...Craig Topper2018-07-141-1/+1
* [DAGCombiner] Set the right SDLoc on a newly-created sextload (6/N)Vedant Kumar2018-05-111-4/+4
* [SelectionDAG] Support some SimplifySetCC cases for comparing against vector ...Craig Topper2018-03-011-27/+13
* [X86] Lower extract_element from k-registers by bitcasting from v16i1 to i16 ...Craig Topper2018-02-281-1/+1
* [X86] Promote 16-bit cmovs to 32-bitsCraig Topper2018-02-201-2/+3
* [X86] Change some compare patterns to use loadi8/loadi16/loadi32/loadi64 help...Craig Topper2018-02-121-2/+1
* [X86] Use min/max for vector ult/ugt compares if avoids a sign flip.Craig Topper2018-02-111-40/+48
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-72/+72
* [X86] Rewrite vXi1 element insertion by using a vXi1 scalar_to_vector and ins...Craig Topper2018-01-231-24/+22
* [X86] Legalize v32i1 without BWI via splitting to v16i1 rather than the defau...Craig Topper2018-01-231-137/+136
* [X86] Use vmovdqu64/vmovdqa64 for unmasked integer vector stores for consiste...Craig Topper2018-01-181-5/+5
* [X86] Use ISD::TRUNCATE instead of X86ISD::VTRUNC when input and output types...Craig Topper2018-01-141-2/+1
* [X86] Make v2i1 and v4i1 legal types without VLXCraig Topper2018-01-071-61/+38
* [X86] In LowerTruncateVecI1, don't add SHL if the input is known to be all si...Craig Topper2018-01-011-1/+0
* [SelectionDAG] Reverse the order of operands in the ISD::ADD created by Targe...Craig Topper2017-12-221-36/+18
* [X86] When lowering insert_vector_elt/extract_vector_elt of vXi1 with a non-c...Craig Topper2017-12-221-62/+30
* [X86] Use SIGN_EXTEND to implement ANY_EXTEND from vXi1.Craig Topper2017-12-221-15/+12
* [X86] Use SIGN_EXTEND rather than ZERO_EXTEND for lowering extract_vector_elt...Craig Topper2017-12-211-4/+4
* [SelectionDAG][X86] Fix insert_vector_elt lowering for v32i1/v64i1 with non-c...Craig Topper2017-12-151-0/+589
* [X86] Don't zero the upper bits of the k-register before extracting a single ...Craig Topper2017-12-141-20/+6
* [X86] Make ANY_EXTEND from vXi1 Custom for more types.Craig Topper2017-12-141-128/+7
* [X86] Handle alls version of vXi1 insert_vector_elt with a constant index wit...Craig Topper2017-12-081-82/+71
* [X86] Fix InsertBitToMaskVector to only issue KSHIFTS of native size so that ...Craig Topper2017-12-071-7/+15
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-52/+52
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-108/+108
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-52/+52
* [X86] Add a pass to convert instruction chains between domains.Guy Blank2017-10-221-10/+8
* [X86][SSE] Add extractps/pextrd equivalence to domain tablesSimon Pilgrim2017-10-211-8/+8
* [X86][AVX512] Regenerate element insertion/extraction testsSimon Pilgrim2017-10-101-352/+171
* [MC] Suppress .Lcfi labels when emitting textual assemblyReid Kleckner2017-10-101-99/+0
* [X86] Use correct subvector index when combining two insert subvectors featur...Craig Topper2017-09-281-0/+11
* [X86][SKX][KNL] Updated regression tests to use -mattr instead of -mcpu flag....Gadi Haber2017-09-271-277/+164
* [X86] Teach the execution domain fixing tables to use movlhps inplace of unpc...Craig Topper2017-09-181-1/+1
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