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* [TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ↵Simon Pilgrim2019-06-251-3/+3
| | | | | | | | | | ZERO/ANY_EXTEND As part of the fix for rL364264 + rL364272 - limit the *_EXTEND conversion to !TLO.LegalOperations || isOperationLegal cases. We'll improve X86 legality in future commits. llvm-svn: 364290
* [X86] Turn X86ISD::VSEXT into X86ISD::VZEXT if the upper bits aren't demanded.Craig Topper2018-11-091-20/+20
| | | | | | | | This makes X86ISD::VSEXT more similar to ISD::SIGN_EXTEND and ISD::ZERO_EXTEND. I'm hoping to replace X86ISD::VSEXT/VZEXT with target independent nodes. Making the target specific nodes similar to the target independent nodes helps minimize test diffs in that patch. llvm-svn: 346539
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-17/+17
| | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
* X86-FMA3: Implemented commute transformation for EVEX/AVX512 FMA3 opcodes.Vyacheslav Klochkov2016-08-111-8/+4
| | | | | | | | | | | This helped to improved memory-folding and register coalescing optimizations. Also, this patch fixed the tracker #17229. Reviewer: Craig Topper. Differential Revision: https://reviews.llvm.org/D23108 llvm-svn: 278431
* [AVX512] Cleanup FMA operand order in patterns to match the VEX versions and ↵Craig Topper2016-07-251-3/+6
| | | | | | to really be 213, 231, and 132. llvm-svn: 276613
* [AVX512] Implement commuting support for EVEX encoded FMA3 instructions.Craig Topper2016-07-231-33/+12
| | | | llvm-svn: 276521
* [AVX512] Use VMOVAPSZ128rr/VMOVAPS256rr for VR128X/VR256X physreg moves when ↵Craig Topper2016-07-181-15/+33
| | | | | | | | VLX is supported. Ideally we would use VEX encoded moves instead of EVEX if the high 16 registers aren't referenced, but this a good first step. llvm-svn: 275763
* AVX-512: Fixed a bug in FMA instruction selection on KNLElena Demikhovsky2016-02-041-10/+5
| | | | | | | | The FMA instruction was selected from AVX2 set instead of AVX-512 Differential Revision: http://reviews.llvm.org/D16884 llvm-svn: 259792
* AVX512: Change VPMOVB2M DAG lowering , use CVT2MASK node instead TRUNCATE.Igor Breger2015-12-271-70/+85
| | | | | | | | | Fix TRUNCATE lowering vector to vector i1, use LSB and not MSB. Implement VPMOVB/W/D/Q2M intrinsic. Differential Revision: http://reviews.llvm.org/D15675 llvm-svn: 256470
* AVX-512: Implemented missing encoding for FMA scalar instructionsIgor Breger2015-07-011-1/+30
| | | | | | | | Added tests for encoding Differential Revision: http://reviews.llvm.org/D10865 llvm-svn: 241159
* AVX-512: Implemented missing encoding and intrinsics for FMA instructionsIgor Breger2015-06-291-7/+82
| | | | | | | | Added tests for DAG lowering ,encoding and intrinsics Differential Revision: http://reviews.llvm.org/D10796 llvm-svn: 240926
* [X86] Accept hasAVX512() as well as hasFMA() when generating FMA.Ahmed Bougacha2015-06-251-1/+1
| | | | | | | | | | We don't always have FMA, for example when using 'clang -mavx512f' without an explicit CPU. Also check for an explicit +avx512f instead of CPUs in a couple related tests. llvm-svn: 240616
* AVX-512: Added FMA instructions.Elena Demikhovsky2013-08-271-0/+83
llvm-svn: 189326
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