| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [X86] When lowering v1i1/v2i1/v4i1/v8i1 load/store with avx512f, but not avx5... | Craig Topper | 2019-01-12 | 1 | -72/+36 |
| * | [x86] allow vector load narrowing with multi-use values | Sanjay Patel | 2018-11-10 | 1 | -236/+142 |
| * | X86 Tests: Update more isel tests with FastVariableShuffle feature | Zvi Rackover | 2018-01-09 | 1 | -18/+18 |
| * | [X86] In LowerTruncateVecI1, don't add SHL if the input is known to be all si... | Craig Topper | 2018-01-01 | 1 | -40/+0 |
| * | [X86] Custom legalize vXi1 extract_subvector with KSHIFTR. | Craig Topper | 2017-12-30 | 1 | -11/+11 |
| * | [X86] Promote v8i1 shuffles to v8i32 instead of v8i64 if we have VLX. | Craig Topper | 2017-12-21 | 1 | -64/+72 |
| * | [CodeGen] Unify MBB reference format in both MIR and debug output | Francis Visoiu Mistrih | 2017-12-04 | 1 | -106/+106 |
| * | Adding test for extraxt sub vector load and store avx512 | Michael Zuckerman | 2017-11-02 | 1 | -0/+1458 |
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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