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path: root/llvm/test/CodeGen/X86/avx512-ext.ll
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* [TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ...Simon Pilgrim2019-06-251-42/+42
* [X86] Allow combinevxi1Bitcast to use pmovmskb on avx512 targets if the input...Craig Topper2019-01-051-27/+6
* [X86] Turn X86ISD::VSEXT into X86ISD::VZEXT if the upper bits aren't demanded.Craig Topper2018-11-091-48/+48
* [X86] Move promotion of vector and/or/xor from legalization to DAG combineCraig Topper2018-10-151-2/+2
* [X86] Add isel pattern for (v8i16 (sext (v8i1))) with DQI and no BWI.Craig Topper2018-09-231-118/+531
* [X86] Remove -mcpu=skx/knl from some tests and use -mattr instead.Craig Topper2018-04-171-16/+24
* [X86] Use vpmovq2m/vpmovd2m for truncate to vXi1 when possible.Craig Topper2018-02-191-18/+18
* [X86] Legalize zero extends from vXi1 to vXi16/vXi32/vXi64 using a sign exten...Craig Topper2018-02-101-8/+13
* [X86] Teach combineExtSetcc to handle ZERO_EXTEND by widening the setcc and t...Craig Topper2018-02-101-45/+21
* [X86] Relax restrictions on what setcc condition codes can be folded with a s...Craig Topper2018-02-051-2/+2
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-32/+32
* [X86] Use vpternlog to implement vector not under AVX512.Craig Topper2018-01-261-2/+2
* [X86] Improve legalization of vXi16/vXi8 selects.Craig Topper2018-01-141-35/+33
* [X86] Make v2i1 and v4i1 legal types without VLXCraig Topper2018-01-071-57/+67
* [X86] Add patterns for using zmm registers for v8i32/v8f32 vselect with the f...Craig Topper2018-01-011-15/+10
* [X86] Remove type restrictions from WidenMaskArithmetic.Craig Topper2017-12-231-15/+6
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-14/+14
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-168/+168
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-14/+14
* [X86][Haswell] Updating HSW instruction scheduling informationGadi Haber2017-08-281-2/+2
* [X86] SET0 to use XMM registers where possible PR26018 PR32862Dinar Temirbulatov2017-07-271-5/+5
* [X86][AVX512] Regenerated and cleaned up extension tests.Simon Pilgrim2017-07-261-184/+184
* [X86][AVX512] Make i1 illegal in the CodeGenGuy Blank2017-05-191-12/+12
* [DAG] add splat vector support for 'and' in SimplifyDemandedBitsSanjay Patel2017-04-191-4/+4
* [AVX-512] Remove explicit KMOVWrk/KMOVWKr instructions from patterns where we...Craig Topper2017-03-291-1/+1
* [AVX-512] Fix accidental uses of AH/BH/CH/DH after copies to/from mask registersCraig Topper2017-03-281-20/+46
* [X86] Generate VZEROUPPER for Skylake-avx512.Amjad Aboud2017-03-031-11/+27
* [X86][AVX512] Add support for ASHR v2i64/v4i64 support without VLXSimon Pilgrim2017-02-201-12/+6
* [SelectionDAG] Teach getNode to simplify a couple easy cases of EXTRACT_SUBVE...Craig Topper2017-01-241-285/+6
* [AVX-512] Change another pattern that was using BLENDM to use masked moves. A...Craig Topper2017-01-091-15/+15
* [AVX-512] Add patterns to use a zero masked VPTERNLOG instruction for vselect...Craig Topper2017-01-091-2/+1
* This is a large patch for X86 AVX-512 of an optimization for reducing code si...Gadi Haber2016-12-281-6/+6
* [X86][AVX512] Add masked VPMOZX test case for PR26762Simon Pilgrim2016-11-131-0/+22
* [TargetLowering] Fix undef vector element issue with true/false result handlingSimon Pilgrim2016-11-081-9/+4
* [AVX-512] Simplify X86InstrInfo::copyPhysReg for 128/256-bit vectors with AVX...Craig Topper2016-09-051-4/+4
* Revert r274613 because it breaks the test suite with AVX512Michael Kuperstein2016-08-251-123/+123
* Revert r279782 due to debug buildbot breakage.Michael Kuperstein2016-08-251-123/+123
* Revert r274613 because it breaks the test suite with AVX512Michael Kuperstein2016-08-251-123/+123
* [AVX512] Fix insertelement i1 lowering.Igor Breger2016-08-141-0/+2
* [AVX512] Fix extractelement i1 lowering.Igor Breger2016-08-111-115/+111
* AVX-512: Changed lowering of BITCAST between i1 vectors and i8/i16/i32 intege...Elena Demikhovsky2016-08-071-6/+0
* [AVX512] Add ExeDomain to vector extend and truncate instructions.Craig Topper2016-07-221-2/+2
* [AVX512] Add initial support for the Execution Domain fixing pass to change s...Craig Topper2016-07-221-4/+4
* [x86][SSE/AVX] optimize pcmp results better (PR28484)Sanjay Patel2016-07-131-7/+5
* [AVX512] Use vpternlog with an immediate of 0xff to create 512-bit all one ve...Craig Topper2016-07-111-2/+4
* VirtRegMap: Replace some identity copies with KILL instructions.Matthias Braun2016-07-091-0/+14
* Re-commit of 274613.Elena Demikhovsky2016-07-061-163/+162
* Reverted 274613 due to compilation failue. Elena Demikhovsky2016-07-061-162/+163
* AVX-512: Optimization for patterns with i1 scalar typeElena Demikhovsky2016-07-061-163/+162
* [X86][AVX512] Add support for PMOVZX masked shuffle commentsSimon Pilgrim2016-07-031-35/+35
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