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path: root/llvm/test/CodeGen/X86/avx512-build-vector.ll
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* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-1/+1
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-1/+1
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-2/+2
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-1/+1
* [X86] SET0 to use XMM registers where possible PR26018 PR32862Dinar Temirbulatov2017-08-031-1/+1
* X86: Do not use llc -march in tests.Matthias Braun2017-08-021-1/+1
* [AVX-512] Correct execution domain for VPERMT2PS and VPERMI2PS.Craig Topper2016-10-161-2/+2
* [DAGCombiner] Teach createBuildVecShuffle to handle cases where input vectors...Craig Topper2016-10-141-5/+5
* [X86][SSE] Enable target shuffle combining to combine multiple shuffle inputs.Simon Pilgrim2016-08-031-7/+4
* [AVX512] Use vpternlog with an immediate of 0xff to create 512-bit all one ve...Craig Topper2016-07-111-3/+4
* Make utils/update_llc_test_checks.py note that the assertions areJames Y Knight2015-11-231-0/+1
* Reverted AVX-512 vector shuffleElena Demikhovsky2015-06-221-10/+0
* AVX-512: Optimized vector shuffle for v16f32 and v16i32 types.Elena Demikhovsky2015-06-011-7/+3
* [opaque pointer type] Add textual IR support for explicit type parameter to l...David Blaikie2015-02-271-1/+1
* [x86] Teach the new vector shuffle lowering how to lower 128-bitChandler Carruth2014-10-051-1/+1
* [x86] Enable the new vector shuffle lowering by default.Chandler Carruth2014-10-041-6/+5
* [x86] Regenerate a bunch more avx512 test cases using my script to haveChandler Carruth2014-10-031-11/+25
* AVX-512: Optimized BUILD_VECTOR pattern; Elena Demikhovsky2014-02-111-0/+12
* AVX-512: added UNPACK instructions and tests for all-zero/all-ones vectorsElena Demikhovsky2013-08-251-0/+18
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