bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Expand)	Author	Age	Files	Lines
*	Followup on Proposal to move MIR physical register namespace to '$' sigil.	Puyan Lotfi	2018-01-31	1	-4/+4
*	[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.	Francis Visoiu Mistrih	2017-12-07	1	-4/+4
*	[CodeGen] Unify MBB reference format in both MIR and debug output	Francis Visoiu Mistrih	2017-12-04	1	-74/+74
*	[CodeGen] Print register names in lowercase in both MIR and debug output	Francis Visoiu Mistrih	2017-11-28	1	-4/+4
*	[X86][SSE] Truncate with PACKSS any input with sufficient sign-bits	Simon Pilgrim	2017-11-01	1	-6/+4
*	[X86][SSE] Add support for lowering shuffles to PACKSS/PACKUS	Simon Pilgrim	2017-10-03	1	-2/+2
*	[X86] SET0 to use XMM registers where possible PR26018 PR32862	Dinar Temirbulatov	2017-07-27	1	-2/+2
*	[X86][AVX2] Dropped -mcpu from avx2 arithmetic/intrinsics tests	Simon Pilgrim	2017-06-28	1	-85/+85
*	[X86] In LowerTRUNCATE, create an ISD::VECTOR_SHUFFLE instead of explicitly c...	Craig Topper	2017-02-05	1	-6/+6
*	[X86][AVX2] Regenerate and add 32-bit tests to core tests	Simon Pilgrim	2016-10-08	1	-122/+424
*	[opaque pointer type] Add textual IR support for explicit type parameter to l...	David Blaikie	2015-02-27	1	-10/+10
*	X86: use vpsllvd (& friends) for 16-bit shifts on Haswell	Tim Northover	2014-02-18	1	-0/+33
*	Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to f...	Stephen Lin	2013-07-14	1	-4/+4
*	Add patterns for v16i16 and v32i8 immAllZerosV to select VPXOR to match v4i64...	Craig Topper	2012-01-13	1	-1/+1
*	Make LowerSIGN_EXTEND_INREG split 256-bit vectors when AVX1 is enabled and us...	Craig Topper	2011-11-21	1	-0/+20
*	Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift instruc...	Craig Topper	2011-11-20	1	-12/+50
*	Add lowering for AVX2 shift instructions.	Craig Topper	2011-11-11	1	-0/+210