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path: root/llvm/test/CodeGen/X86/avx2-masked-gather.ll
Commit message (Expand)AuthorAgeFilesLines
* [X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm inste...Craig Topper2019-07-021-3/+3
* [MIR] Add simple PRE pass to MachineCSEAnton Afanasyev2019-06-091-28/+20
* [DAGCombiner] Replace gathers with a zero mask with the passthru valueBenjamin Kramer2019-05-291-0/+21
* Revert r361356: "[MIR] Add simple PRE pass to MachineCSE"David L. Jones2019-05-271-20/+28
* [MIR] Add simple PRE pass to MachineCSEAnton Afanasyev2019-05-221-28/+20
* Revert "[MIR] Add simple PRE pass to MachineCSE"Anton Afanasyev2019-05-031-20/+28
* [MIR] Add simple PRE pass to MachineCSEAnton Afanasyev2019-05-031-28/+20
* [ScalarizeMaskedMemIntrin] When expanding masked gathers, start with the pass...Craig Topper2018-09-271-197/+161
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-12/+12
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-80/+80
* [X86] Custom legalize v2i32 gathers via widening rather than promoting.Craig Topper2017-12-011-16/+14
* [X86][SelectionDAG] Make sure we explicitly sign extend the index when type p...Craig Topper2017-12-011-4/+4
* [X86] Add a DAG combine to simplify masks for AVX2 gather instructions.Craig Topper2017-12-011-40/+10
* [X86] Optimize avx2 vgatherqps for v2f32 with v2i64 index type.Craig Topper2017-11-301-8/+6
* [X86] Make sure we don't remove sign extends of masks with AVX2 masked gathers.Craig Topper2017-11-301-4/+48
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-12/+12
* [X86] Don't report gather is legal on Skylake CPUs when AVX2/AVX512 is disabl...Craig Topper2017-11-251-0/+480
* [LV][X86] Support of AVX2 Gathers code generation and update the LV with thisMohammed Agabaria2017-11-201-735/+137
* [X86][Codegen] adding masked gathers tests for avx2Mohammed Agabaria2017-09-181-0/+915
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