| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [X86][AVX2] Dropped -mcpu from avx2 arithmetic/intrinsics tests | Simon Pilgrim | 2017-06-28 | 1 | -17/+17 |
| | | | | | | | Use triple and attribute only for consistency llvm-svn: 306531 | ||||
| * | [x86] transform vector inc/dec to use -1 constant (PR33483) | Sanjay Patel | 2017-06-26 | 1 | -12/+16 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert vector increment or decrement to sub/add with an all-ones constant: add X, <1, 1...> --> sub X, <-1, -1...> sub X, <1, 1...> --> add X, <-1, -1...> The all-ones vector constant can be materialized using a pcmpeq instruction that is commonly recognized as an idiom (has no register dependency), so that's better than loading a splat 1 constant. AVX512 uses 'vpternlogd' for 512-bit vectors because there is apparently no better way to produce 512 one-bits. The general advantages of this lowering are: 1. pcmpeq has lower latency than a memop on every uarch I looked at in Agner's tables, so in theory, this could be better for perf, but... 2. That seems unlikely to affect any OOO implementation, and I can't measure any real perf difference from this transform on Haswell or Jaguar, but... 3. It doesn't look like it from the diffs, but this is an overall size win because we eliminate 16 - 64 constant bytes in the case of a vector load. If we're broadcasting a scalar load (which might itself be a bug), then we're replacing a scalar constant load + broadcast with a single cheap op, so that should always be smaller/better too. 4. This makes the DAG/isel output more consistent - we use pcmpeq already for padd x, -1 and psub x, -1, so we should use that form for +1 too because we can. If there's some reason to favor a constant load on some CPU, let's make the reverse transform for all of these cases (either here in the DAG or in a later machine pass). This should fix: https://bugs.llvm.org/show_bug.cgi?id=33483 Differential Revision: https://reviews.llvm.org/D34336 llvm-svn: 306289 | ||||
| * | [X86][AVX2] Regenerate and add 32-bit tests to core tests | Simon Pilgrim | 2016-10-08 | 1 | -20/+82 |
| | | | | | llvm-svn: 283666 | ||||
| * | [X86] Extract PSIGN/BLENDVP tests into vector-blend.ll. NFC. | Ahmed Bougacha | 2016-02-16 | 1 | -29/+0 |
| | | | | | | | | | | | We're going to stop generating PSIGN, so calling a test "psign" isn't ideal. Instead, call these tests what they really are: variable blends using logic. Also add a test to exhibit a case we're currently missing in the PSIGN combine. llvm-svn: 261022 | ||||
| * | Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to ↵ | Stephen Lin | 2013-07-14 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280 | ||||
| * | X86: Match pmin/pmax as a target specific dag combine. This occurs during ↵ | Benjamin Kramer | 2012-12-21 | 1 | -3/+2 |
| | | | | | | | | | vectorization. Part of PR14667. llvm-svn: 170908 | ||||
| * | Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled. | Craig Topper | 2011-11-19 | 1 | -0/+12 |
| | | | | | llvm-svn: 145004 | ||||
| * | Extend VPBLENDVB and VPSIGN lowering to work for AVX2. | Craig Topper | 2011-11-19 | 1 | -0/+29 |
| | | | | | llvm-svn: 144987 | ||||
| * | Add lowering for AVX2 shift instructions. | Craig Topper | 2011-11-11 | 1 | -73/+0 |
| | | | | | llvm-svn: 144380 | ||||
| * | AVX2: Add patterns for variable shift operations | Nadav Rotem | 2011-11-09 | 1 | -2/+73 |
| | | | | | llvm-svn: 144212 | ||||
| * | Add AVX2 support for vselect of v32i8 | Nadav Rotem | 2011-11-09 | 1 | -0/+19 |
| | | | | | llvm-svn: 144187 | ||||
| * | Enable execution dependency fix pass for YMM registers when AVX2 is enabled. ↵ | Craig Topper | 2011-11-09 | 1 | -0/+38 |
| Add AVX2 logical operations to list of replaceable instructions. llvm-svn: 144179 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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