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path: root/llvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll
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* [x86] add movddup specialization for build vector lowering (PR37502) Sanjay Patel2018-12-211-6/+3
* [X86] Add patterns for vector and/or/xor/andn with other types than vXi64.Craig Topper2018-10-221-1/+4
* [X86] Merge the FR128 and VR128 regclass since they have identical spill and ...Craig Topper2018-07-161-26/+26
* [X86][AVX] Regenerate AVX1 fast-isel tests. Simon Pilgrim2018-07-091-1900/+1181
* [X86] Lowering sqrt intrinsics to native IRTomasz Krupa2018-06-151-6/+10
* [X86] Remove 128/256-bit cvtdq2ps, cvtudq2ps, cvtqq2pd, cvtuqq2pd intrinsics.Craig Topper2018-05-211-2/+1
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-28/+28
* [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBL...Simon Pilgrim2018-01-151-6/+6
* [X86][SSE] Match PSHUFLW/PSHUFHW + PSHUFD vXi16 shuffle patterns (PR34686)Simon Pilgrim2017-12-291-4/+4
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-28/+28
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-380/+380
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-28/+28
* [X86][SSE] Add extractps/pextrd equivalence to domain tablesSimon Pilgrim2017-10-211-4/+4
* [X86FixupBWInsts] More precise register liveness if no <imp-use> on MOVs.Nikolai Bozhenov2017-09-181-54/+54
* [X86] Teach the execution domain fixing tables to use movlhps inplace of unpc...Craig Topper2017-09-181-8/+8
* [X86] Teach execution domain fixing to convert between VPERMILPS and VPSHUFD.Craig Topper2017-09-181-2/+2
* [X86] Remove usages of vperm2f intrinsics from fast isel tests to match what ...Craig Topper2017-09-151-3/+3
* [X86] Add patterns to turn an insert into lower subvector of a zero vector in...Craig Topper2017-09-031-18/+6
* [X86] Canonicalize (concat_vectors X, zero) -> (insert_subvector zero, X, 0).Craig Topper2017-09-031-8/+8
* [X86] SET0 to use XMM registers where possible PR26018 PR32862Dinar Temirbulatov2017-07-271-8/+8
* Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB."Hans Wennborg2017-05-181-26/+26
* [x86, SSE] AVX1 PR28129 (256-bit all-ones rematerialization)Simon Pilgrim2017-05-131-4/+4
* Add LiveRangeShrink pass to shrink live range within BB.Dehao Chen2017-05-121-26/+26
* [X86][AVX] Added codegen tests for _mm256_zext* helper intrinsics (PR32839)Simon Pilgrim2017-04-291-0/+54
* [X86] Revert r299387 due to AVX legalization infinite loop.Michael Kuperstein2017-04-061-3/+6
* [X86][SSE]] Lower BUILD_VECTOR with repeated elts as BUILD_VECTOR + VECTOR_SH...Simon Pilgrim2017-04-031-6/+3
* [x86] don't blindly transform SETB into SBBSanjay Patel2017-03-121-20/+20
* [X86] Cleanup 'x' and 'y' mnemonic suffixes for vcvtpd2dq/vcvttpd2dq/vcvtpd2p...Craig Topper2016-11-141-6/+6
* [DAGCombine] Avoid INSERT_SUBVECTOR reinsertions (PR28678)Simon Pilgrim2016-08-101-2/+1
* [X86][AVX] Added support for lowering to VBROADCASTF128/VBROADCASTI128 (reapp...Simon Pilgrim2016-07-221-6/+4
* [X86][SSE] Reimplement SSE fp2si conversion intrinsics instead of using gener...Simon Pilgrim2016-07-191-2/+4
* [X86][AVX] Add VBROADCASTF128/VBROADCASTI128 shuffle comments supportSimon Pilgrim2016-07-141-4/+4
* VirtRegMap: Replace some identity copies with KILL instructions.Matthias Braun2016-07-091-0/+28
* Recommit r274692 - [X86] Transform setcc + movzbl into xorl + setccMichael Kuperstein2016-07-071-20/+20
* Revert r274692 to check whether this is what breaks windows selfhost.Michael Kuperstein2016-07-071-20/+20
* [X86] Transform setcc + movzbl into xorl + setccMichael Kuperstein2016-07-061-20/+20
* [CodeGen] Make the code that detects a if a shuffle is really a concatenation...Craig Topper2016-07-041-6/+0
* [X86][SSE] Added support for combining target shuffles to (V)PSHUFD/VPERMILPD...Simon Pilgrim2016-06-281-3/+3
* [X86][SSE] Replace (V)CVTTPS2DQ and VCVTTPD2DQ truncating (round to zero) f32...Simon Pilgrim2016-06-021-4/+2
* [X86][SSE] Updated storeu fast-isel tests to match clang builtin testsSimon Pilgrim2016-05-301-19/+14
* [X86][SSE] Updated (V)CVTDQ2PD(Y) and (V)CVTPS2PD(Y) fast-isel codegen to mat...Simon Pilgrim2016-05-231-4/+2
* [x86, AVX] don't add a vzeroupper if that's what the code is already doing (P...Sanjay Patel2016-05-221-4/+0
* [X86][AVX] Sync with clang/test/CodeGen/avx-builtins.cSimon Pilgrim2016-05-201-211/+3303
* [X86][SSE] Fixed issue with commutation of 'faux unary' target shuffles (PR26...Simon Pilgrim2016-02-201-0/+2
* [X86][AVX] Added fast-isel intrinsics testsSimon Pilgrim2016-02-191-0/+675
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