| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [DAGCombiner] reduce extract subvector of concat | Sanjay Patel | 2020-01-09 | 1 | -7/+5 |
| * | [X86] Pass v32i16/v64i8 in zmm registers on KNL target. | Craig Topper | 2019-08-30 | 1 | -2/+5 |
| * | [X86] Teach lowerV4I32Shuffle to only use broadcasts if the mask has more tha... | Craig Topper | 2019-08-19 | 1 | -4/+4 |
| * | Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization... | Craig Topper | 2019-08-07 | 1 | -486/+993 |
| * | Revert "[X86] Enable -x86-experimental-vector-widening-legalization by default." | Mitch Phillips | 2019-08-06 | 1 | -993/+486 |
| * | [X86] Enable -x86-experimental-vector-widening-legalization by default. | Craig Topper | 2019-08-05 | 1 | -486/+993 |
| * | [X86] When using AND+PACKUS in lowerV16I8Shuffle, generate the build vector d... | Craig Topper | 2019-07-22 | 1 | -1/+1 |
| * | [X86][AVX] combineExtractSubvector - 'little to big' extract_subvector(bitcas... | Simon Pilgrim | 2019-06-26 | 1 | -2/+2 |
| * | [x86] split 256-bit store of concatenated vectors | Sanjay Patel | 2019-06-04 | 1 | -210/+192 |
| * | Revert "[x86] split 256-bit store of concatenated vectors" | Sanjay Patel | 2019-05-28 | 1 | -192/+210 |
| * | [x86] split 256-bit store of concatenated vectors | Sanjay Patel | 2019-05-28 | 1 | -210/+192 |
| * | [X86][AVX] Fold concat(packus(),packus()) -> packus(concat(),concat()) (PR34773) | Simon Pilgrim | 2019-05-07 | 1 | -56/+52 |
| * | [X86] Use INSERT_SUBREG rather than SUBREG_TO_REG when creating LEA64_32 duri... | Craig Topper | 2019-04-04 | 1 | -86/+88 |
| * | [X86][SSE] detectAVGPattern - Match zext(or(x,y)) 'add like' patterns (PR41316) | Simon Pilgrim | 2019-03-30 | 1 | -59/+7 |
| * | [X86][SSE] Add PAVG test case from PR41316 | Simon Pilgrim | 2019-03-30 | 1 | -0/+80 |
| * | [X86][AVX] Start shuffle combining from ZERO_EXTEND_VECTOR_INREG (PR40685) | Simon Pilgrim | 2019-03-24 | 1 | -54/+56 |
| * | [X86] Add SimplifyDemandedBitsForTargetNode support for PINSRB/PINSRW | Simon Pilgrim | 2019-03-15 | 1 | -172/+172 |
| * | [x86] narrow a shuffle that doesn't use or set any high elements | Sanjay Patel | 2019-01-25 | 1 | -102/+103 |
| * | [LegalizeVectorTypes] Don't use SplitVecOp_TruncateHelper if we're heading to... | Craig Topper | 2018-11-23 | 1 | -725/+382 |
| * | [LegalizeVectorTypes] Have SplitVecOp_TruncateHelper fall back to SplitVecOp_... | Craig Topper | 2018-11-22 | 1 | -22/+7 |
| * | [X86] Lower v16i16->v8i16 truncate using an 'and' with 255, an extract_subvec... | Craig Topper | 2018-11-18 | 1 | -28/+28 |
| * | [x86] allow vector load narrowing with multi-use values | Sanjay Patel | 2018-11-10 | 1 | -390/+312 |
| * | [X86] Don't emit *_extend_vector_inreg nodes when both the input and output t... | Craig Topper | 2018-11-02 | 1 | -172/+160 |
| * | Revert r345165 "[X86] Bring back the MOV64r0 pseudo instruction" | Craig Topper | 2018-10-31 | 1 | -223/+232 |
| * | [X86] Bring back the MOV64r0 pseudo instruction | Craig Topper | 2018-10-24 | 1 | -232/+223 |
| * | [X86] Add 128 MOVDDUP to the constant pool printing in X86AsmPrinter::EmitIns... | Craig Topper | 2018-10-15 | 1 | -2/+4 |
| * | [X86][AVX1] Enable *_EXTEND_VECTOR_INREG lowering of 256-bit vectors | Simon Pilgrim | 2018-10-09 | 1 | -6/+6 |
| * | [X86][AVX2] Enable ZERO_EXTEND_VECTOR_INREG lowering of 256-bit vectors | Simon Pilgrim | 2018-10-08 | 1 | -55/+46 |
| * | [X86] Handle COPYs of physregs better (regalloc hints) | Simon Pilgrim | 2018-09-19 | 1 | -5/+5 |
| * | [X86] Don't create ZERO_EXTEND_INREG/SIGN_EXTEND_INREG for v1iX vectors. | Craig Topper | 2018-09-07 | 1 | -15/+4 |
| * | [X86] Don't create X86ISD::AVG nodes from v1iX vectors. | Craig Topper | 2018-09-07 | 1 | -0/+40 |
| * | [X86][SSE] Consistently prefer lowering to PACKUS over PACKSS | Simon Pilgrim | 2018-06-08 | 1 | -12/+12 |
| * | [DAGCombiner] Change the SDLoc on split extloads (2/N) | Vedant Kumar | 2018-05-01 | 1 | -92/+91 |
| * | [DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N) | Vedant Kumar | 2018-05-01 | 1 | -117/+116 |
| * | [test] Update llc checks for CodeGen/X86/avg.ll | Vedant Kumar | 2018-04-24 | 1 | -170/+170 |
| * | [DAG, X86] Revert r327197 "Revert r327170, r327171, r327172" | Nirav Dave | 2018-03-19 | 1 | -57/+57 |
| * | Revert "[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"" | Nirav Dave | 2018-03-17 | 1 | -57/+57 |
| * | [DAG, X86] Revert r327197 "Revert r327170, r327171, r327172" | Nirav Dave | 2018-03-17 | 1 | -57/+57 |
| * | [X86] Post process the DAG after isel to remove vector moves that were added ... | Craig Topper | 2018-03-16 | 1 | -1/+0 |
| * | [LegalizeTypes] In SplitVecOp_TruncateHelper, use GetSplitVector on the input... | Craig Topper | 2018-03-13 | 1 | -328/+165 |
| * | Revert: r327172 "Correct load-op-store cycle detection analysis" | Nirav Dave | 2018-03-10 | 1 | -57/+57 |
| * | Improve Dependency analysis when doing multi-node Instruction Selection | Nirav Dave | 2018-03-09 | 1 | -57/+57 |
| * | [TargetLowering] Add vector BITCAST support to SimplifyDemandedVectorElts | Simon Pilgrim | 2018-03-06 | 1 | -147/+137 |
| * | Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" | Geoff Berry | 2018-02-27 | 1 | -1/+1 |
| * | [X86] Don't use getZExtValue when we have no idea how large the input element... | Craig Topper | 2018-02-26 | 1 | -0/+1049 |
| * | [X86] Remove VT.isSimple() check from detectAVGPattern. | Craig Topper | 2018-02-26 | 1 | -0/+372 |
| * | [DAG, X86] Revert r324797, r324491, and r324359. | Chandler Carruth | 2018-02-17 | 1 | -57/+57 |
| * | [DAG, X86] Improve Dependency analysis when doing multi-node | Nirav Dave | 2018-02-06 | 1 | -57/+57 |
| * | [X86] Use vmovdqu64/vmovdqa64 for unmasked integer vector stores for consiste... | Craig Topper | 2018-01-18 | 1 | -6/+6 |
| * | [X86][SSE] Split large PAVGB/PAVGW vectors to legal widths | Simon Pilgrim | 2017-12-21 | 1 | -2288/+283 |
