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path: root/llvm/test/CodeGen/X86/add-sub-nsw-nuw.ll
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* [DAGCombiner] re-enable truncation of binopsSanjay Patel2018-12-081-1/+1
* [DAGCombiner] disable truncation of binops by defaultSanjay Patel2018-12-071-1/+1
* [DAGCombiner] narrow truncated binopsSanjay Patel2018-11-291-1/+1
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-1/+1
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-1/+1
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-1/+1
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-1/+1
* [x86] regenerate checks with update_llc_test_checks.pySanjay Patel2017-06-121-2/+1
* [DAG] disable nsw/nuw for add/sub/mul when simplifying based on demanded bits...Sanjay Patel2016-10-311-0/+25
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