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* [WebAssembly] Added test for inline assembly roundtrip.Wouter van Oortmerssen2018-10-231-0/+43
| | | | | | | | | | | | | | | | | | | Summary: Due to previous work to make WebAssembly MC by default stack-only inline assembly now "just works" (previously it didn't since it had no way to know types of registers), so no further work required. So far we only have tests (in inline-asm.ll) which test with non-existing instructions, so this adds a test that roundtrips both the inline assembly and its surrounding code thru the assembler. Reviewers: dschuff, sunfish Subscribers: sbc100, jgravelle-google, eraman, aheejin, llvm-commits Differential Revision: https://reviews.llvm.org/D52914 llvm-svn: 344977
* [WebAssembly] Implement vector sext_inreg and tests with comparisonsThomas Lively2018-10-202-20/+875
| | | | | | | | | | | | Summary: Depends on D53251. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53252 llvm-svn: 344826
* [WebAssembly] Custom lower i64x2 constant shifts to avoid wrapThomas Lively2018-10-201-3/+26
| | | | | | | | | | | | Summary: Depends on D53057. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53251 llvm-svn: 344825
* [WebAssembly] Handle undefined lane indices in SIMD patternsThomas Lively2018-10-191-0/+266
| | | | | | | | | | | | | | | | Summary: Undefined indices in shuffles can be used when not all lanes of the output vector will be used. This happens for example in the expansion of vector reduce operations. Regardless, undefs are legal as lane indices in IR and should be supported. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53057 llvm-svn: 344803
* Revert "[WebAssembly] LSDA info generation"Krasimir Georgiev2018-10-162-242/+3
| | | | | | | | This reverts commit r344575. Newly introduced test eh-lsda.ll.test fails with use-after-free under ASAN build. llvm-svn: 344639
* [WebAssembly] LSDA info generationHeejin Ahn2018-10-162-3/+242
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This adds support for LSDA (exception table) generation for wasm EH. Wasm EH mostly follows the structure of Itanium-style exception tables, with one exception: a call site table entry in wasm EH corresponds to not a call site but a landing pad. In wasm EH, the VM is responsible for stack unwinding. After an exception occurs and the stack is unwound, the control flow is transferred to wasm 'catch' instruction by the VM, after which the personality function is called from the compiler-generated code. (Refer to WasmEHPrepare pass for more information on this part.) This patch: - Changes wasm.landingpad.index intrinsic to take a token argument, to make this 1:1 match with a catchpad instruction - Stores landingpad index info and catch type info MachineFunction in before instruction selection - Lowers wasm.lsda intrinsic to an MCSymbol pointing to the start of an exception table - Adds WasmException class with overridden methods for table generation - Adds support for LSDA section in Wasm object writer Reviewers: dschuff, sbc100, rnk Subscribers: mgorny, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52748 llvm-svn: 344575
* [WebAssembly] SIMD min and maxThomas Lively2018-10-133-12/+204
| | | | | | | | | | | | Summary: Depends on D52324 and D52764. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52325 llvm-svn: 344438
* [WebAssembly] Saturating float to int intrinsicsThomas Lively2018-10-112-0/+136
| | | | | | | | | | | | | | | | Summary: Although the saturating float to int instructions are already emitted from normal IR, the fpto{s,u}i instructions produce poison values if the argument cannot fit in the result type. These intrinsics are therefore necessary to get guaranteed defined saturating behavior. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53004 llvm-svn: 344204
* [WebAssembly] Fix fneg loweringThomas Lively2018-10-101-2/+4
| | | | | | | | | | | | | | Summary: Subtraction from zero and floating point negation do not have the same semantics, so fix lowering. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52948 llvm-svn: 344107
* [WebAssembly] Handle V128 register class in explicit locals passThomas Lively2018-10-091-0/+4
| | | | | | | | | | | | | | Summary: Also add tests to catch crashes in passes that are not normally run in tests. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52959 llvm-svn: 344094
* [WebAssembly] Saturating arithmetic intrinsicsThomas Lively2018-10-052-4/+108
| | | | | | | | | | | | Summary: Depends on D52805. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52813 llvm-svn: 343833
* [WebAssembly] Ignore DBG_VALUE in WebAssemblyCFGStackify pass when looking ↵Yury Delendik2018-10-041-0/+48
| | | | | | | | | | | | | | | | | | | for block start Summary: Fixes https://bugs.llvm.org/show_bug.cgi?id=39158 and regression caused by D49034. Though it is possible the problem was existed before and was exposed by additional DBG_VALUEs. Reviewers: sunfish, dschuff, aheejin Reviewed By: aheejin Subscribers: sbc100, aheejin, llvm-commits, alexcrichton, jgravelle-google Differential Revision: https://reviews.llvm.org/D52837 llvm-svn: 343827
* [WebAssembly] Bitselect intrinsic and instructionThomas Lively2018-10-032-7/+171
| | | | | | | | | | | | Summary: Depends on D52755. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52805 llvm-svn: 343739
* [WebAssembly] any_true and all_true intrinsics and instructionsThomas Lively2018-10-031-0/+109
| | | | | | | | | | Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52755 llvm-svn: 343649
* [WebAssembly] Stop generating helper functions in ↵Sam Clegg2018-10-022-27/+6
| | | | | | | | | | | | | | | | | | | | | | | | | WebAssemblyLowerEmscriptenEHSjLj Previously we were creating weakly defined helper function in each translation unit: - setThrew - setTempRet0 Instead we now assume these will be provided at link time. In emscripten they are provided in compiler-rt: https://github.com/kripken/emscripten/pull/7203 Additionally we previously created three global variable which are also now required to exist at link time instead. - __THREW__ - _threwValue - __tempRet0 Differential Revision: https://reviews.llvm.org/D49208 llvm-svn: 343640
* [WebAssembly] Restore slashes in SIMD conversion namesThomas Lively2018-10-021-20/+20
| | | | | | | | | | | | Summary: Depends on D52372 and D52442. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52512 llvm-svn: 343558
* [WebAssembly] SIMD conversionsThomas Lively2018-09-261-0/+100
| | | | | | | | | | | | | | | | Summary: Lowers (s|u)itofp and fpto(s|u)i instructions for vectors. The fp to int conversions produce poison values if their arguments are out of the convertible range, so a future CL will have to add an LLVM intrinsic to make the saturating behavior of this conversion usable. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52372 llvm-svn: 343052
* [WebAssembly] SIMD sqrtThomas Lively2018-09-251-0/+24
| | | | | | | | | | Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52387 llvm-svn: 342937
* [WebAssembly][NFC] Fix hardcoded stack indices in testsThomas Lively2018-09-241-4/+4
| | | | | | | | | | Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52388 llvm-svn: 342928
* [WebAssembly][NFC] Rename simd-conversions test to simd-bitcastsThomas Lively2018-09-211-0/+0
| | | | | | | | | | | | | | Summary: This name is more accurate and I want to reuse the simd-conversions name for testing the actual conversion ops. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52333 llvm-svn: 342761
* [WebAssembly][NFC] Add missing tests for indirect callsThomas Lively2018-09-201-0/+33
| | | | | | | | | | | | Summary: Depends on D52105. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52254 llvm-svn: 342691
* [WebAssembly] Add V128 value type to binary formatThomas Lively2018-09-201-2/+23
| | | | | | | | | | | | | | Summary: Adds the necessary support to lib/ObjectYAML and fixes SIMD calls to allow the tests to work. Also removes some dead code that would otherwise have to have been updated. Reviewers: aheejin, dschuff, sbc100 Subscribers: jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52105 llvm-svn: 342689
* [WebAssembly] v4f32.abs and v2f64.absThomas Lively2018-09-181-0/+25
| | | | | | | | | | Summary: implement lowering of @llvm.fabs for vector types. Reviewers: aheejin, dschuff Subscribers: llvm-svn: 342513
* [WebAssembly][NFC] Generalize operand numbers in SIMD testsThomas Lively2018-09-154-522/+522
| | | | | | | | | | Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52130 llvm-svn: 342303
* [WebAssembly] SIMD shiftsThomas Lively2018-09-151-0/+265
| | | | | | | | | | | | | | | | | Summary: Implement shifts of vectors by i32. Since LLVM defines shifts as binary operations between two vectors, this involves pattern matching on splatted shift operands. For v2i64 shifts any i32 shift operands have to be zero extended in the input and any i64 shift operands have to be wrapped in the output. Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51906 llvm-svn: 342302
* [WebAssembly] SIMD negThomas Lively2018-09-141-0/+69
| | | | | | | | | | | | Summary: Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52009 llvm-svn: 342296
* [WebAssembly][NFC] Move SIMD encoding tests to dedicated fileThomas Lively2018-09-145-1109/+983
| | | | | | | | | | | | | | | | Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
* [WebAssembly][NFC] Fix unconventional test namesThomas Lively2018-09-145-0/+0
| | | | | | | | | | Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52110 llvm-svn: 342273
* [WebAssembly] Fix signature of `main` in FixFunctionBitcastsSam Clegg2018-09-132-0/+16
| | | | | | | | | Also, add a check to ensure that when main has the expected signature we do not create a wrapper. Differential Revision: https://reviews.llvm.org/D51562 llvm-svn: 342157
* [WebAssembly] Make tied inline asm operands work againHeejin Ahn2018-09-121-0/+9
| | | | | | | | | | | | | | | | | Summary: rL341389 broke code with tied register operands in inline assembly. For example, `asm("" : "=r"(var) : "0"(var));` The code above specifies the input operand to be in the same register with the output operand, tying the two register. This patch makes this kind of code work again. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, eraman, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51991 llvm-svn: 342084
* [WebAssembly] SIMD comparisonsThomas Lively2018-09-121-0/+644
| | | | | | | | | | | | | | | | Summary: Match the ordering semantics of non-vector comparisons. For floating point comparisons that do not correspond to instructions, the tests check that some vector comparison instruction was emitted but do not care about the full implementation. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51765 llvm-svn: 342064
* [WebAssembly] v8x16.shuffleThomas Lively2018-09-071-0/+96
| | | | | | | | | | | | | | | | | | Summary: Since the shuffle mask is not exposed as an operand in the native ISel DAG, create a new WebAssembly ISD node exposing the mask. The mask is lowered as sixteen immediate byte indices no matter what type the original vector shuffle was operating on. This CL depends on D51656 Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51659 llvm-svn: 341718
* [WebAssembly][NFC] Add colon to label in testThomas Lively2018-09-041-1/+1
| | | | llvm-svn: 341414
* [WebAssembly][NFC] Fix formatting and testsThomas Lively2018-09-041-6/+8
| | | | | | | | | | | | Summary: Small fixes Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51656 llvm-svn: 341411
* [WebAssembly] Fix operand rewriting in inline asm lowering.Dan Gohman2018-09-041-1/+1
| | | | | | | | | | | Use MachineOperand::ChangeToImmediate rather than reassigning MachineOperands to new values created from MachineOperand::CreateImm, so that their parent pointers are preserved. This fixes "Instruction has operand with wrong parent set" errors reported by the MachineVerifier. llvm-svn: 341389
* [WebAssembly] Vector conversionsThomas Lively2018-08-301-0/+324
| | | | | | | | | | | | | | Summary: Lowers away bitconverts between vector types. This CL depends on D51383. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51498 llvm-svn: 341128
* [WebAssembly] SIMD loads and storesThomas Lively2018-08-301-0/+1312
| | | | | | | | | | | | Summary: Reuse the patterns from WebAssemblyInstrMemory.td. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51383 llvm-svn: 341127
* [WebAssembly] Be a little more conservative in WebAssemblyFixFunctionBitcastsSam Clegg2018-08-302-15/+68
| | | | | | | | | | | | | | We don't have enough information to know if struct types being bitcast will cause validation failures or not, so be conservative and allow such cases to persist (fot now). Fixes: https://bugs.llvm.org/show_bug.cgi?id=38711 Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51460 llvm-svn: 341010
* [WebAssembly][NFC] Fix up SIMD bitwise testsThomas Lively2018-08-281-12/+15
| | | | | | | | | | | | | | Summary: The updated tests were previously infallible because the SIMD bitwise operations do not contain vector types in their names. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51369 llvm-svn: 340858
* [WebAssembly] v128.notThomas Lively2018-08-281-0/+49
| | | | | | Implementation and tests. llvm-svn: 340857
* [WebAssembly] Added default stack-only instruction mode for MC.Wouter van Oortmerssen2018-08-2783-110/+306
| | | | | | | | | | | | | | | | | | | | | Summary: Made it convert from register to stack based instructions, and removed the registers. Fixes to related code that was expecting register based instructions. Added the correct testing flag to all tests, depending on what the format they were expecting so far. Translated one test to stack format as example: reg-stackify-stack.ll tested: llvm-lit -v `find test -name WebAssembly` unittests/MC/* Reviewers: dschuff, sunfish Subscribers: sbc100, jgravelle-google, eraman, aheejin, llvm-commits, jfb Differential Revision: https://reviews.llvm.org/D51241 llvm-svn: 340750
* [WebAssembly] Prioritize splats over v128.constsThomas Lively2018-08-231-0/+35
| | | | | | | | | | | | | | Summary: Splats are fewer bytes than v128.consts, so use them when either could apply. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51179 llvm-svn: 340569
* [WebAssembly] SIMD Bitwise binary arithmeticThomas Lively2018-08-231-0/+132
| | | | | | | | | | | | Summary: AND, OR, and XOR. This CL depends on D51113. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51136 llvm-svn: 340505
* [WebAssembly] Arbitrary BUILD_VECTOR and remove i64x2.mulThomas Lively2018-08-222-4/+136
| | | | | | | | | | | | | | | | | | Summary: This CL adds support for arbitrary BUILD_VECTORS, i.e. not splats and not consts. This is the last feature needed to properly lower v2i64 multiplies without a i64x2.mul instruction (which is not in the spec), so i64x2.mul is removed as well. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51082 Remove unnecessary condition and fix whitespace llvm-svn: 340472
* [WebAssembly] Don't write SP back when prolog is generated only for EHHeejin Ahn2018-08-221-0/+29
| | | | | | | | | | | | | | | Summary: When we don't actually have stack-allocated variables but need SP only to support EH, we don't need to write SP back in the epilog, because we don't bump down the stack pointer. Reviewers: dschuff Subscribers: jgravelle-google, sbc100, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51114 llvm-svn: 340454
* [WebAssembly] Restore __stack_pointer after catch instructionsHeejin Ahn2018-08-211-0/+5
| | | | | | | | | | | | | | | Summary: After the stack is unwound due to a thrown exception, the `__stack_pointer` global can point to an invalid address. This inserts instructions that restore `__stack_pointer` global. Reviewers: jgravelle-google, dschuff Subscribers: mgorny, sbc100, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50980 llvm-svn: 340339
* [WebAssembly] v128.constThomas Lively2018-08-211-0/+72
| | | | | | | | | | | | | | | | Summary: This CL implements v128.const for each vector type. New operand types are added to ensure the vector contents can be serialized without LEB encoding. Tests are added for instruction selection, encoding, assembly and disassembly. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50873 llvm-svn: 340336
* [WebAssembly] Don't make wasm cleanuppads into funclet entriesHeejin Ahn2018-08-211-2/+1
| | | | | | | | | | | | | | | Summary: Catchpads and cleanuppads are not funclet entries; they are only EH scope entries. We already dont't set `isEHFuncletEntry` for catchpads. This patch does the same thing for cleanuppads. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50654 llvm-svn: 340330
* [WebAssembly] Add isEHScopeReturn instruction propertyHeejin Ahn2018-08-211-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | Summary: So far, `isReturn` property is used to mean both a return instruction from a functon and the end of an EH scope, a scope that starts with a EH scope entry BB and ends with a catchret or a cleanupret instruction. Because WinEH uses funclets, all EH-scope-ending instructions are also real return instruction from a function. But for wasm, they only serve as the end marker of an EH scope but not a return instruction that exits a function. This mismatch caused incorrect prolog and epilog generation in wasm EH scopes. This patch fixes this. This patch is in the same vein with rL333045, which splits `MachineBasicBlock::isEHFuncletEntry` into `isEHFuncletEntry` and `isEHScopeEntry`. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50653 llvm-svn: 340325
* [WebAssembly] Revert type of wake count in atomic.wake to i32Heejin Ahn2018-08-201-25/+25
| | | | | | | | | | | | | | Summary: We decided to revert this from i64 to i32 in Nov 28 CG meeting. Fixes PR38632. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D51010 llvm-svn: 340234
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