Commit message (Collapse) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | [ARM] MVE big endian loads/stores | David Green | 2019-08-08 | 1 | -58/+142 |
| | | | | | | | | | | | This adds some missing patterns for big endian loads/stores, allowing unaligned loads/stores to also be selected with an extra VREV, which produces better code than aligning through a stack. Also moves VLDR_P0 to not be LE only, and adjusts some of the tests to show all that working. Differential Revision: https://reviews.llvm.org/D65583 llvm-svn: 368304 | ||||
* | [ARM] MVE predicate register support | David Green | 2019-07-24 | 1 | -0/+81 |
This adds support code for building and shuffling i1 predicate registers. It generally uses two basic principles, either converting the predicate into an scalar (through a PREDICATE_CAST) and doing scalar operations on it there, or by converting the register to an full vector register and back. Some of the code here is a not super efficient but will hopefully cover most cases of moving i1 vectors around and can be improved in subsequent patches. Some code by David Sherwood. Differential Revision: https://reviews.llvm.org/D65052 llvm-svn: 366890 |