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* Add back tests for empty function in SPARC and PowerPC.Rafael Espindola2014-09-151-0/+32
| | | | llvm-svn: 217834
* Fix a lot of confusion around inserting nops on empty functions.Rafael Espindola2014-09-151-8/+0
| | | | | | | | | | | | | | | | On MachO, and MachO only, we cannot have a truly empty function since that breaks the linker logic for atomizing the section. When we are emitting a frame pointer, the presence of an unreachable will create a cfi instruction pointing past the last instruction. This is perfectly fine. The FDE information encodes the pc range it applies to. If some tool cannot handle this, we should explicitly say which bug we are working around and only work around it when it is actually relevant (not for ELF for example). Given the unreachable we could omit the .cfi_def_cfa_register, but then again, we could also omit the entire function prologue if we wanted to. llvm-svn: 217801
* Provide an implementation of getNoopForMachoTarget for SPARC.Brad Smith2014-09-111-0/+8
| | | | llvm-svn: 217611
* IR: add "cmpxchg weak" variant to support permitted failure.Tim Northover2014-06-131-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a weak variant of the cmpxchg operation, as described in C++11. A cmpxchg instruction with this modifier is permitted to fail to store, even if the comparison indicated it should. As a result, cmpxchg instructions must return a flag indicating success in addition to their original iN value loaded. Thus, for uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The second flag is 1 when the store succeeded. At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been added as the natural representation for the new cmpxchg instructions. It is a strong cmpxchg. By default this gets Expanded to the existing ATOMIC_CMP_SWAP during Legalization, so existing backends should see no change in behaviour. If they wish to deal with the enhanced node instead, they can call setOperationAction on it. Beware: as a node with 2 results, it cannot be selected from TableGen. Currently, no use is made of the extra information provided in this patch. Test updates are almost entirely adapting the input IR to the new scheme. Summary for out of tree users: ------------------------------ + Legacy Bitcode files are upgraded during read. + Legacy assembly IR files will be invalid. + Front-ends must adapt to different type for "cmpxchg". + Backends should be unaffected by default. llvm-svn: 210903
* Reduce verbiage of lit.local.cfg filesAlp Toker2014-06-091-2/+1
| | | | | | We can just split targets_to_build in one place and make it immutable. llvm-svn: 210496
* TableGen: fix operand counting for aliasesTim Northover2014-05-168-24/+24
| | | | | | | | | | | | | | | | | | | | | TableGen has a fairly dubious heuristic to decide whether an alias should be printed: does the alias have lest operands than the real instruction. This is bad enough (particularly with no way to override it), but it should at least be calculated consistently for both strings. This patch implements that logic: first get the *correct* string for the variant, in the same way as the Matcher, without guessing; then count the number of whitespace chars. There are basically 4 changes this brings about after the previous commits; all of these appear to be good, so I have changed the tests: + ARM64: we print "neg X, Y" instead of "sub X, xzr, Y". + ARM64: we skip implicit "uxtx" and "uxtw" modifiers. + Sparc: we print "mov A, B" instead of "or %g0, A, B". + Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B" llvm-svn: 208969
* Allow sret on the second parameter as well as the firstReid Kleckner2014-05-091-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | MSVC always places the implicit sret parameter after the implicit this parameter of instance methods. We used to handle this for x86_thiscallcc by allocating the sret parameter on the stack and leaving the this pointer in ecx, but that doesn't handle alternative calling conventions like cdecl, stdcall, fastcall, or the win64 convention. Instead, change the verifier to allow sret on the second parameter. This also requires changing the Mips and X86 backends to return the argument with the sret parameter, instead of assuming that the sret parameter comes first. The Sparc backend also returns sret parameters in a register, but I wasn't able to update it to handle secondary sret parameters. It currently calls report_fatal_error if you feed it an sret in the second parameter. Reviewers: rafael.espindola, majnemer Differential Revision: http://reviews.llvm.org/D3617 llvm-svn: 208453
* Remove the -disable-cfi option.Rafael Espindola2014-05-051-34/+0
| | | | | | | This also add a release note about it. If this stays I will cleanup MC next week. llvm-svn: 207977
* Revert "blockfreq: Temporarily turn on -debug-only=block-freq"Duncan P. N. Exon Smith2014-04-191-3/+2
| | | | | | This reverts commit r206705, as planned. llvm-svn: 206706
* blockfreq: Temporarily turn on -debug-only=block-freqDuncan P. N. Exon Smith2014-04-191-2/+3
| | | | | | | | | | | These tests fail after my BlockFrequencyInfo rewrite on two buildbots [1][2]. I can't reproduce it locally, so I'm temporarily turning on -debug-only=block-freq so I can find the problem. [1]: http://bb.pgr.jp/builders/ninja-x64-msvc-RA-centos6/builds/1860 [2]: http://llvm-amd64.freebsd.your.org/b/builders/clang-i386-freebsd/builds/18477 llvm-svn: 206705
* Add some target triples for better determinismDuncan P. N. Exon Smith2014-04-181-0/+1
| | | | | | | | | These tests were failing on some buildbots after r206548 (reverted in r206556), but passing locally. They were missing target triples, so maybe that's the problem? llvm-svn: 206621
* Remove the linker_private and linker_private_weak linkages.Rafael Espindola2014-03-132-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These linkages were introduced some time ago, but it was never very clear what exactly their semantics were or what they should be used for. Some investigation found these uses: * utf-16 strings in clang. * non-unnamed_addr strings produced by the sanitizers. It turns out they were just working around a more fundamental problem. For some sections a MachO linker needs a symbol in order to split the section into atoms, and llvm had no idea that was the case. I fixed that in r201700 and it is now safe to use the private linkage. When the object ends up in a section that requires symbols, llvm will use a 'l' prefix instead of a 'L' prefix and things just work. With that, these linkages were already dead, but there was a potential future user in the objc metadata information. I am still looking at CGObjcMac.cpp, but at this point I am convinced that linker_private and linker_private_weak are not what they need. The objc uses are currently split in * Regular symbols (no '\01' prefix). LLVM already directly provides whatever semantics they need. * Uses of a private name (start with "\01L" or "\01l") and private linkage. We can drop the "\01L" and "\01l" prefixes as soon as llvm agrees with clang on L being ok or not for a given section. I have two patches in code review for this. * Uses of private name and weak linkage. The last case is the one that one could think would fit one of these linkages. That is not the case. The semantics are * the linker will merge these symbol by *name*. * the linker will hide them in the final DSO. Given that the merging is done by name, any of the private (or internal) linkages would be a bad match. They allow llvm to rename the symbols, and that is really not what we want. From the llvm point of view, these objects should really be (linkonce|weak)(_odr)?. For now, just keeping the "\01l" prefix is probably the best for these symbols. If we one day want to have a more direct support in llvm, IMHO what we should add is not a linkage, it is just a hidden_symbol attribute. It would be applicable to multiple linkages. For example, on weak it would produce the current behavior we have for objc metadata. On internal, it would be equivalent to private (and we should then remove private). llvm-svn: 203866
* IR: add a second ordering operand to cmpxhg for failureTim Northover2014-03-111-2/+2
| | | | | | | | | | | | | | | The syntax for "cmpxchg" should now look something like: cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic where the second ordering argument gives the required semantics in the case that no exchange takes place. It should be no stronger than the first ordering constraint and cannot be either "release" or "acq_rel" (since no store will have taken place). rdar://problem/15996804 llvm-svn: 203559
* [Sparc] Add support for parsing directives in SparcAsmParser.Venkatraman Govindaraju2014-03-011-2/+0
| | | | llvm-svn: 202564
* [Sparc] Emit 'restore' instead of 'restore %g0, %g0, %g0'. This improves the ↵Venkatraman Govindaraju2014-03-012-3/+6
| | | | | | readability of the generated code. llvm-svn: 202563
* Lower FNEG just like FABS to fneg[ds] and fmov[ds], thus avoidingRoman Divacky2014-02-271-0/+11
| | | | | | | expensive libcall. Also, Qp_neg is not implemented on at least FreeBSD. This is also what gcc is doing. llvm-svn: 202422
* SPARC: Implement TRAP lowering. Matches what GCC emits.Benjamin Kramer2014-02-231-0/+11
| | | | llvm-svn: 201994
* Expand 64bit {SHL,SHR,SRA}_PARTS on sparcv9.Roman Divacky2014-02-191-0/+14
| | | | llvm-svn: 201718
* [Sparc] Remove spurious checks from a testcase.Venkatraman Govindaraju2014-02-191-2/+0
| | | | llvm-svn: 201690
* Re-commit: Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove ↵Daniel Sanders2014-02-131-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hasRawTextSupport() call Summary: AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output. The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as. All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler. Changes since review (and last commit attempt): - Fixed test failures that were missed due to configuration of local build. (fixes crash.ll and a couple others). - Fixed tests that happened to pass because the local build was on X86 (should fix 2007-12-17-InvokeAsm.ll) - mature-mc-support.ll's should no longer require all targets to be compiled. (should fix ARM and PPC buildbots) - Object output (-filetype=obj and similar) now forces the integrated assembler to be enabled regardless of default setting or -no-integrated-as. (should fix SystemZ buildbots) Reviewers: rafael Reviewed By: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2686 llvm-svn: 201333
* [Sparc] Emit relocations for Thread Local Storage (TLS) when integrated ↵Venkatraman Govindaraju2014-02-071-0/+48
| | | | | | assembler is used. llvm-svn: 200962
* [Sparc] Emit correct relocations for PIC code when integrated assembler is used.Venkatraman Govindaraju2014-02-071-0/+33
| | | | llvm-svn: 200961
* [Sparc] Set %o7 as the return address register instead of %i7 in ↵Venkatraman Govindaraju2014-02-011-0/+8
| | | | | | MCRegisterInfo. Also, add CFI instructions to initialize the frame correctly. llvm-svn: 200617
* Implement SPARCv9 atomic_swap_64 with a pseudo.Jakob Stoklund Olesen2014-01-301-0/+9
| | | | | | | | The SWAP instruction only exists in a 32-bit variant, but the 64-bit atomic swap can be implemented in terms of CASX, like the other atomic rmw primitives. llvm-svn: 200453
* [Sparc] Use %r_disp32 for pc_rel entries in FDE as well.Venkatraman Govindaraju2014-01-291-0/+2
| | | | | | This makes MCAsmInfo::getExprForFDESymbol() a virtual function and overrides it in SparcMCAsmInfo. llvm-svn: 200376
* [Sparc] Use %r_disp32 for pc_rel entries in gcc_except_table and eh_frame.Venkatraman Govindaraju2014-01-291-2/+27
| | | | | | | | Otherwise, assembler (gas) fails to assemble them with error message "operation combines symbols in different segments". This is because MC computes pc_rel entries with subtract expression between labels from different sections. llvm-svn: 200373
* [SparcV9] Use correct register class (I64RegClass) to hold the address of ↵Venkatraman Govindaraju2014-01-291-2/+38
| | | | | | _GLOBAL_OFFSET_TABLE_ in sparcv9. llvm-svn: 200368
* Fix the DWARF EH encodings for Sparc PIC code.Jakob Stoklund Olesen2014-01-281-17/+61
| | | | | | | Also emit the stubs that were generated for references to typeinfo symbols. llvm-svn: 200282
* Clean up the Legal/Expand logic for SPARC popc.Jakob Stoklund Olesen2014-01-261-2/+2
| | | | llvm-svn: 200141
* Only generate the popc instruction for SPARC CPUs that implement it.Jakob Stoklund Olesen2014-01-261-6/+6
| | | | | | | The popc instruction is defined in the SPARCv9 instruction set architecture, but it was emulated on CPUs older than Niagara 2. llvm-svn: 200131
* Fix swapped CASA operands.Jakob Stoklund Olesen2014-01-261-2/+2
| | | | | | Found by SingleSource/UnitTests/AtomicOps.c llvm-svn: 200130
* Implement atomicrmw operations in 32 and 64 bits for SPARCv9.Jakob Stoklund Olesen2014-01-241-1/+82
| | | | | | These all use the compare-and-swap CASA/CASXA instructions. llvm-svn: 199975
* [Sparc] Add support for inline assembly constraints which specify registers ↵Venkatraman Govindaraju2014-01-221-0/+10
| | | | | | by their aliases. llvm-svn: 199786
* [Sparc] Add support for inline assembly constraint 'I'. Venkatraman Govindaraju2014-01-221-0/+35
| | | | llvm-svn: 199781
* [Sparc] Do not add PC to _GLOBAL_OFFSET_TABLE_ address to access GOT in ↵Venkatraman Govindaraju2014-01-221-4/+2
| | | | | | | | absolute code. Fixes PR#18521 llvm-svn: 199775
* Always let value types influence register classes.Jakob Stoklund Olesen2014-01-141-0/+25
| | | | | | | | | | | | | | | | | | | | | When creating a virtual register for a def, the value type should be used to pick the register class. If we only use the register class constraint on the instruction, we might pick a too large register class. Some registers can store values of different sizes. For example, the x86 xmm registers can hold f32, f64, and 128-bit vectors. The three different value sizes are represented by register classes with identical register sets: FR32, FR64, and VR128. These register classes have different spill slot sizes, so it is important to use the right one. The register class constraint on an instruction doesn't necessarily care about the size of the value its defining. The value type determines that. This fixes a problem where InstrEmitter was picking 32-bit register classes for 64-bit values on SPARC. llvm-svn: 199187
* Handle bundled terminators in isBlockOnlyReachableByFallthrough.Jakob Stoklund Olesen2014-01-121-0/+23
| | | | | | | | | | Targets like SPARC and MIPS have delay slots and normally bundle the delay slot instruction with the corresponding terminator. Teach isBlockOnlyReachableByFallthrough to find any MBB operands on bundled terminators so SPARC doesn't need to specialize this function. llvm-svn: 199061
* The SPARCv9 ABI returns a float in %f0.Jakob Stoklund Olesen2014-01-123-8/+8
| | | | | | | | | | | | | | | This is different from the argument passing convention which puts the first float argument in %f1. With this patch, all returned floats are treated as if the 'inreg' flag were set. This means multiple float return values get packed in %f0, %f1, %f2, ... Note that when returning a struct in registers, clang will set the 'inreg' flag on the return value, so that behavior is unchanged. This also happens when returning a float _Complex. llvm-svn: 199028
* [Sparc] Add missing processor types: v7 and niagaraVenkatraman Govindaraju2014-01-111-1/+8
| | | | llvm-svn: 199024
* Fix broken CHECK lines.Benjamin Kramer2014-01-111-1/+1
| | | | llvm-svn: 199016
* [Sparc] Bundle instruction with delay slow and its filler. Now, we can use ↵Venkatraman Govindaraju2014-01-111-2/+2
| | | | | | -verify-machineinstrs with SPARC backend. llvm-svn: 199014
* [Sparc] Emit retl/ret instead of jmp instruction. It improves the ↵Venkatraman Govindaraju2014-01-1010-46/+46
| | | | | | readability of the assembly generated. llvm-svn: 198910
* [SparcV9]: Implement RETURNADDR and FRAMEADDR lowering in SPARC64. Venkatraman Govindaraju2014-01-041-11/+24
| | | | | | Fixes PR18356. llvm-svn: 198480
* [Sparc] Handle atomic loads/stores in sparc backend.Venkatraman Govindaraju2014-01-011-0/+63
| | | | llvm-svn: 198286
* [SparcV9]: Custom lower UMULO/SMULO so that the arguments are send to ↵Venkatraman Govindaraju2014-01-011-0/+5
| | | | | | __multi3() in correct order. llvm-svn: 198281
* [SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL ↵Venkatraman Govindaraju2014-01-011-2/+16
| | | | | | does not clear top 32 bit, only SRL does. llvm-svn: 198280
* [SparcV9] Use separate instruction patterns for 64 bit arithmetic ↵Venkatraman Govindaraju2013-12-291-0/+116
| | | | | | | | instructions instead of reusing 32 bit instruction patterns. This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot. llvm-svn: 198157
* [SparcV9] For codegen generated library calls that return float, set inreg ↵Venkatraman Govindaraju2013-12-291-0/+21
| | | | | | | | flag manually in LowerCall(). This makes the sparc backend to generate Sparc64 ABI compliant code. llvm-svn: 198149
* [SparcV9]: Implement lowering of long double (fp128) arguments in Sparc64 ABI.Venkatraman Govindaraju2013-12-291-0/+30
| | | | | | Also, pass fp128 arguments to varargs through integer registers if necessary. llvm-svn: 198145
* [Sparc] Lower and MachineInstr to MC and print assembly using MCInstPrinter.Venkatraman Govindaraju2013-12-261-1/+1
| | | | llvm-svn: 198030
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