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| author | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2014-01-22 01:29:51 +0000 |
|---|---|---|
| committer | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2014-01-22 01:29:51 +0000 |
| commit | 407e442245b5515c5f110f81b7c1e3f90c40c68c (patch) | |
| tree | df1b6fc462b96acccb9420448b52fa19139a7cba /llvm/test/CodeGen/SPARC | |
| parent | bbf322b0bb87ba9717c2c474aa30eea933e29661 (diff) | |
| download | bcm5719-llvm-407e442245b5515c5f110f81b7c1e3f90c40c68c.tar.gz bcm5719-llvm-407e442245b5515c5f110f81b7c1e3f90c40c68c.zip | |
[Sparc] Add support for inline assembly constraint 'I'.
llvm-svn: 199781
Diffstat (limited to 'llvm/test/CodeGen/SPARC')
| -rw-r--r-- | llvm/test/CodeGen/SPARC/inlineasm.ll | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/SPARC/inlineasm.ll b/llvm/test/CodeGen/SPARC/inlineasm.ll new file mode 100644 index 00000000000..7ecdd670666 --- /dev/null +++ b/llvm/test/CodeGen/SPARC/inlineasm.ll @@ -0,0 +1,35 @@ +; RUN: llc -march=sparc <%s | FileCheck %s + +; CHECK-LABEL: test_constraint_r +; CHECK: add %o1, %o0, %o0 +define i32 @test_constraint_r(i32 %a, i32 %b) { +entry: + %0 = tail call i32 asm sideeffect "add $2, $1, $0", "=r,r,r"(i32 %a, i32 %b) + ret i32 %0 +} + +; CHECK-LABEL: test_constraint_I +; CHECK: add %o0, 1023, %o0 +define i32 @test_constraint_I(i32 %a) { +entry: + %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 1023) + ret i32 %0 +} + +; CHECK-LABEL: test_constraint_I_neg +; CHECK: add %o0, -4096, %o0 +define i32 @test_constraint_I_neg(i32 %a) { +entry: + %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 -4096) + ret i32 %0 +} + +; CHECK-LABEL: test_constraint_I_largeimm +; CHECK: sethi 9, [[R0:%[gilo][0-7]]] +; CHECK: or [[R0]], 784, [[R1:%[gilo][0-7]]] +; CHECK: add %o0, [[R1]], %o0 +define i32 @test_constraint_I_largeimm(i32 %a) { +entry: + %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 10000) + ret i32 %0 +} |
