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* [Sparc] Remove spurious checks from a testcase.Venkatraman Govindaraju2014-02-191-2/+0
| | | | llvm-svn: 201690
* Re-commit: Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove ↵Daniel Sanders2014-02-131-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hasRawTextSupport() call Summary: AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output. The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as. All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler. Changes since review (and last commit attempt): - Fixed test failures that were missed due to configuration of local build. (fixes crash.ll and a couple others). - Fixed tests that happened to pass because the local build was on X86 (should fix 2007-12-17-InvokeAsm.ll) - mature-mc-support.ll's should no longer require all targets to be compiled. (should fix ARM and PPC buildbots) - Object output (-filetype=obj and similar) now forces the integrated assembler to be enabled regardless of default setting or -no-integrated-as. (should fix SystemZ buildbots) Reviewers: rafael Reviewed By: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2686 llvm-svn: 201333
* [Sparc] Emit relocations for Thread Local Storage (TLS) when integrated ↵Venkatraman Govindaraju2014-02-071-0/+48
| | | | | | assembler is used. llvm-svn: 200962
* [Sparc] Emit correct relocations for PIC code when integrated assembler is used.Venkatraman Govindaraju2014-02-071-0/+33
| | | | llvm-svn: 200961
* [Sparc] Set %o7 as the return address register instead of %i7 in ↵Venkatraman Govindaraju2014-02-011-0/+8
| | | | | | MCRegisterInfo. Also, add CFI instructions to initialize the frame correctly. llvm-svn: 200617
* Implement SPARCv9 atomic_swap_64 with a pseudo.Jakob Stoklund Olesen2014-01-301-0/+9
| | | | | | | | The SWAP instruction only exists in a 32-bit variant, but the 64-bit atomic swap can be implemented in terms of CASX, like the other atomic rmw primitives. llvm-svn: 200453
* [Sparc] Use %r_disp32 for pc_rel entries in FDE as well.Venkatraman Govindaraju2014-01-291-0/+2
| | | | | | This makes MCAsmInfo::getExprForFDESymbol() a virtual function and overrides it in SparcMCAsmInfo. llvm-svn: 200376
* [Sparc] Use %r_disp32 for pc_rel entries in gcc_except_table and eh_frame.Venkatraman Govindaraju2014-01-291-2/+27
| | | | | | | | Otherwise, assembler (gas) fails to assemble them with error message "operation combines symbols in different segments". This is because MC computes pc_rel entries with subtract expression between labels from different sections. llvm-svn: 200373
* [SparcV9] Use correct register class (I64RegClass) to hold the address of ↵Venkatraman Govindaraju2014-01-291-2/+38
| | | | | | _GLOBAL_OFFSET_TABLE_ in sparcv9. llvm-svn: 200368
* Fix the DWARF EH encodings for Sparc PIC code.Jakob Stoklund Olesen2014-01-281-17/+61
| | | | | | | Also emit the stubs that were generated for references to typeinfo symbols. llvm-svn: 200282
* Clean up the Legal/Expand logic for SPARC popc.Jakob Stoklund Olesen2014-01-261-2/+2
| | | | llvm-svn: 200141
* Only generate the popc instruction for SPARC CPUs that implement it.Jakob Stoklund Olesen2014-01-261-6/+6
| | | | | | | The popc instruction is defined in the SPARCv9 instruction set architecture, but it was emulated on CPUs older than Niagara 2. llvm-svn: 200131
* Fix swapped CASA operands.Jakob Stoklund Olesen2014-01-261-2/+2
| | | | | | Found by SingleSource/UnitTests/AtomicOps.c llvm-svn: 200130
* Implement atomicrmw operations in 32 and 64 bits for SPARCv9.Jakob Stoklund Olesen2014-01-241-1/+82
| | | | | | These all use the compare-and-swap CASA/CASXA instructions. llvm-svn: 199975
* [Sparc] Add support for inline assembly constraints which specify registers ↵Venkatraman Govindaraju2014-01-221-0/+10
| | | | | | by their aliases. llvm-svn: 199786
* [Sparc] Add support for inline assembly constraint 'I'. Venkatraman Govindaraju2014-01-221-0/+35
| | | | llvm-svn: 199781
* [Sparc] Do not add PC to _GLOBAL_OFFSET_TABLE_ address to access GOT in ↵Venkatraman Govindaraju2014-01-221-4/+2
| | | | | | | | absolute code. Fixes PR#18521 llvm-svn: 199775
* Always let value types influence register classes.Jakob Stoklund Olesen2014-01-141-0/+25
| | | | | | | | | | | | | | | | | | | | | When creating a virtual register for a def, the value type should be used to pick the register class. If we only use the register class constraint on the instruction, we might pick a too large register class. Some registers can store values of different sizes. For example, the x86 xmm registers can hold f32, f64, and 128-bit vectors. The three different value sizes are represented by register classes with identical register sets: FR32, FR64, and VR128. These register classes have different spill slot sizes, so it is important to use the right one. The register class constraint on an instruction doesn't necessarily care about the size of the value its defining. The value type determines that. This fixes a problem where InstrEmitter was picking 32-bit register classes for 64-bit values on SPARC. llvm-svn: 199187
* Handle bundled terminators in isBlockOnlyReachableByFallthrough.Jakob Stoklund Olesen2014-01-121-0/+23
| | | | | | | | | | Targets like SPARC and MIPS have delay slots and normally bundle the delay slot instruction with the corresponding terminator. Teach isBlockOnlyReachableByFallthrough to find any MBB operands on bundled terminators so SPARC doesn't need to specialize this function. llvm-svn: 199061
* The SPARCv9 ABI returns a float in %f0.Jakob Stoklund Olesen2014-01-123-8/+8
| | | | | | | | | | | | | | | This is different from the argument passing convention which puts the first float argument in %f1. With this patch, all returned floats are treated as if the 'inreg' flag were set. This means multiple float return values get packed in %f0, %f1, %f2, ... Note that when returning a struct in registers, clang will set the 'inreg' flag on the return value, so that behavior is unchanged. This also happens when returning a float _Complex. llvm-svn: 199028
* [Sparc] Add missing processor types: v7 and niagaraVenkatraman Govindaraju2014-01-111-1/+8
| | | | llvm-svn: 199024
* Fix broken CHECK lines.Benjamin Kramer2014-01-111-1/+1
| | | | llvm-svn: 199016
* [Sparc] Bundle instruction with delay slow and its filler. Now, we can use ↵Venkatraman Govindaraju2014-01-111-2/+2
| | | | | | -verify-machineinstrs with SPARC backend. llvm-svn: 199014
* [Sparc] Emit retl/ret instead of jmp instruction. It improves the ↵Venkatraman Govindaraju2014-01-1010-46/+46
| | | | | | readability of the assembly generated. llvm-svn: 198910
* [SparcV9]: Implement RETURNADDR and FRAMEADDR lowering in SPARC64. Venkatraman Govindaraju2014-01-041-11/+24
| | | | | | Fixes PR18356. llvm-svn: 198480
* [Sparc] Handle atomic loads/stores in sparc backend.Venkatraman Govindaraju2014-01-011-0/+63
| | | | llvm-svn: 198286
* [SparcV9]: Custom lower UMULO/SMULO so that the arguments are send to ↵Venkatraman Govindaraju2014-01-011-0/+5
| | | | | | __multi3() in correct order. llvm-svn: 198281
* [SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL ↵Venkatraman Govindaraju2014-01-011-2/+16
| | | | | | does not clear top 32 bit, only SRL does. llvm-svn: 198280
* [SparcV9] Use separate instruction patterns for 64 bit arithmetic ↵Venkatraman Govindaraju2013-12-291-0/+116
| | | | | | | | instructions instead of reusing 32 bit instruction patterns. This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot. llvm-svn: 198157
* [SparcV9] For codegen generated library calls that return float, set inreg ↵Venkatraman Govindaraju2013-12-291-0/+21
| | | | | | | | flag manually in LowerCall(). This makes the sparc backend to generate Sparc64 ABI compliant code. llvm-svn: 198149
* [SparcV9]: Implement lowering of long double (fp128) arguments in Sparc64 ABI.Venkatraman Govindaraju2013-12-291-0/+30
| | | | | | Also, pass fp128 arguments to varargs through integer registers if necessary. llvm-svn: 198145
* [Sparc] Lower and MachineInstr to MC and print assembly using MCInstPrinter.Venkatraman Govindaraju2013-12-261-1/+1
| | | | llvm-svn: 198030
* [SPARCV9]: Adjust the resultant pointer of DYNAMIC_STACKALLOC with the stack ↵Venkatraman Govindaraju2013-12-091-1/+1
| | | | | | BIAS on sparcV9. llvm-svn: 196755
* [Sparc]: Implement getSetCCResultType() in SparcTargetLowering so that ↵Venkatraman Govindaraju2013-12-091-0/+14
| | | | | | umulo/smulo can be lowered on sparcv9 without an assertion error. llvm-svn: 196751
* [SparcV9]: Expand MULHU/MULHS:i64 and UMUL_LOHI/SMUL_LOHI:i64 on sparcv9.Venkatraman Govindaraju2013-12-081-0/+16
| | | | | | This fixes PR18150. llvm-svn: 196735
* [Sparc] Emit large negative adjustments to SP/FP with sethi+xor instead of ↵Venkatraman Govindaraju2013-11-241-0/+21
| | | | | | sethi+or. This generates correct code for both sparc32 and sparc64. llvm-svn: 195576
* [SparcV9]: Do not emit .register directives for global registers that are ↵Venkatraman Govindaraju2013-11-241-2/+0
| | | | | | clobbered by calls but not used in the function itself. llvm-svn: 195574
* [SparcV9] Enable custom lowering of DYNAMIC_STACKALLOC in sparc64.Venkatraman Govindaraju2013-11-241-6/+16
| | | | llvm-svn: 195573
* [SparcV9] Handle i64 <-> float conversions in sparcv9 mode.Venkatraman Govindaraju2013-11-032-1/+232
| | | | llvm-svn: 193957
* [Sparc] Expand FP_TO_UINT, UINT_TO_FP for fp128.Venkatraman Govindaraju2013-11-031-0/+32
| | | | llvm-svn: 193947
* [SparcV9] Add ctpop instruction for i64. Also, expand ctlz, cttz and bswap.Venkatraman Govindaraju2013-11-031-0/+23
| | | | llvm-svn: 193941
* SparcV9 doesnt have rem instruction either.Roman Divacky2013-10-311-0/+23
| | | | llvm-svn: 193789
* [Sparc] Disable tail call optimization for sparc64.Venkatraman Govindaraju2013-10-091-0/+40
| | | | | | This patch fixes PR17506. llvm-svn: 192294
* [Sparc] Do not emit nop after fcmp* instruction with V9.Venkatraman Govindaraju2013-10-062-0/+5
| | | | llvm-svn: 192056
* [Sparc] Custom lower addc/adde/subc/sube on i64 in sparc64.Venkatraman Govindaraju2013-10-061-0/+11
| | | | | | This is required because i64 is a legal type but addxcc/subxcc reads icc carry bit, which are 32 bit conditional codes. llvm-svn: 192054
* [Sparc] Use addxcc/subxcc for adde/sube instead of addx/subx.Venkatraman Govindaraju2013-10-061-0/+39
| | | | | | addx/subx does not modify conditional codes whereas addxcc/subxx does. llvm-svn: 192053
* [Sparc] Use correct alignment while loading/storing fp128 values.Venkatraman Govindaraju2013-10-051-0/+21
| | | | llvm-svn: 192023
* [Sparc] Respect hasHardQuad parameter correctly when lowering SINT_TO_FP ↵Venkatraman Govindaraju2013-10-051-0/+13
| | | | | | with fp128 operand. llvm-svn: 192015
* [Sparc] Correct the floating point conditional code mapping in ↵Venkatraman Govindaraju2013-10-041-0/+32
| | | | | | GetOppositeBranchCondition(). llvm-svn: 192006
* TBAA: update tbaa format from scalar format to struct-path aware format.Manman Ren2013-09-301-6/+8
| | | | llvm-svn: 191690
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