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path: root/llvm/test/CodeGen/RISCV/setcc-logic.ll
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* [RISCV] Switch to the Machine SchedulerLuis Marques2019-09-171-14/+14
| | | | | | | | | Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
* Revert Patch from PhabricatorLuis Marques2019-09-171-14/+14
| | | | | | This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) llvm-svn: 372104
* Patch from PhabricatorLuis Marques2019-09-171-14/+14
| | | | llvm-svn: 372092
* [RISCV] Update setcc-logic.ll codegen testLuis Marques2019-03-261-12/+8
| | | | | | This should have been updated as part of D59753. llvm-svn: 357002
* [RISCV] Allow conversion of CC logic to bitwise logicAlex Bradbury2019-03-221-0/+130
Indicates in the TargetLowering interface that conversions from CC logic to bitwise logic are allowed. Adds tests that show the benefit when optimization opportunities are detected. Also adds tests that show that when the optimization is not applied correct code is generated (but opportunities for other optimizations remain). Differential Revision: https://reviews.llvm.org/D59596 Patch by Luís Marques. llvm-svn: 356740
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