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* [RISCV] Switch to the Machine SchedulerLuis Marques2019-09-171-10/+10
| | | | | | | | | Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
* Revert Patch from PhabricatorLuis Marques2019-09-171-10/+10
| | | | | | This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) llvm-svn: 372104
* Patch from PhabricatorLuis Marques2019-09-171-10/+10
| | | | llvm-svn: 372092
* [RISCV] Add RV64F codegen supportAlex Bradbury2019-01-311-0/+21
| | | | | | | | | | | | | This requires a little extra work due tothe fact i32 is not a legal type. When call lowering happens post-legalisation (e.g. when an intrinsic was inserted during legalisation). A bitcast from f32 to i32 can't be introduced. This is similar to the challenges with RV32D. To handle this, we introduce target-specific DAG nodes that perform bitcast+anyext for f32->i64 and trunc+bitcast for i64->f32. Differential Revision: https://reviews.llvm.org/D53235 llvm-svn: 352807
* [RISCV] Add codegen for RV32F floating point load/storeAlex Bradbury2018-03-201-0/+27
As part of this, add support for load/store from the constant pool. This is used to materialise f32 constants. llvm-svn: 327979
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