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path: root/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
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* [RISCV] Add RV64F codegen supportAlex Bradbury2019-01-311-0/+23
| | | | | | | | | | | | | This requires a little extra work due tothe fact i32 is not a legal type. When call lowering happens post-legalisation (e.g. when an intrinsic was inserted during legalisation). A bitcast from f32 to i32 can't be introduced. This is similar to the challenges with RV32D. To handle this, we introduce target-specific DAG nodes that perform bitcast+anyext for f32->i64 and trunc+bitcast for i64->f32. Differential Revision: https://reviews.llvm.org/D53235 llvm-svn: 352807
* [RISCV] Add another potential combine to {double,float}-bitmanip-dagcombines.llAlex Bradbury2019-01-251-1/+55
| | | | | | | | (fcopysign a, (fneg b)) will be expanded to bitwise operations by DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN if the floating point type isn't legal. Arguably it might be worth doing a combine even if it is legal. llvm-svn: 352240
* [RISCV] Add tests to demonstrate bitcasted fneg/fabs dagcombinesAlex Bradbury2019-01-251-0/+49
This target-independent code won't trigger for cases such as RV32FD where custom SelectionDAG nodes are generated. These new tests demonstrate such cases. Additionally, float-arith.ll was updated so that fneg.s, fsgnjn.s, and fabs.s selection patterns are actually exercised. llvm-svn: 352199
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