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* [RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bitsAlex Bradbury2018-04-181-2/+0
| | | | | | | These immediates can be materialised with just an lui, rather than an lui+addi pair. llvm-svn: 330293
* Revert "[RISCV] implement li pseudo instruction"Alex Bradbury2018-04-181-0/+2
| | | | | | | | | Reverts rL330224, while issues with the C extension and missed common subexpression elimination opportunities are addressed. Neither of these issues are visible in current RISC-V backend unit tests, which clearly need expanding. llvm-svn: 330281
* [RISCV] implement li pseudo instructionAlex Bradbury2018-04-171-2/+0
| | | | | | | | | | | | | | The implementation follows the MIPS backend and expands the pseudo instruction directly during asm parsing. As the result, only real MC instructions are emitted to the MCStreamer. Additionally, PseudoLI instructions are emitted during codegen. The actual expansion to real instructions is performed during MI to MC lowering and is similar to the expansion performed by the GNU Assembler. Differential Revision: https://reviews.llvm.org/D41949 Patch by Mario Werner. llvm-svn: 330224
* [RISCV] Add codegen for RV32F arithmetic and conversion operationsAlex Bradbury2018-03-201-0/+190
Currently, only a soft floating point ABI is supported. llvm-svn: 327976
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