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* [RISCV] Switch to the Machine SchedulerLuis Marques2019-09-171-3/+3
| | | | | | | | | Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
* Revert Patch from PhabricatorLuis Marques2019-09-171-3/+3
| | | | | | This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) llvm-svn: 372104
* Patch from PhabricatorLuis Marques2019-09-171-3/+3
| | | | llvm-svn: 372092
* [RISCV] Implement RV64D codegenAlex Bradbury2019-02-011-0/+180
| | | | | | | | | | | | This patch: * Adds necessary RV64D codegen patterns * Modifies CC_RISCV so it will properly handle f64 types (with soft float ABI) Note that in general there is no reason to try to select fcvt.w[u].d rather than fcvt.l[u].d for i32 conversions because fptosi/fptoui produce poison if the input won't fit into the target type. Differential Revision: https://reviews.llvm.org/D53237 llvm-svn: 352833
* [RISCV] Codegen support for RV32D floating point conversion operationsAlex Bradbury2018-04-121-0/+89
This also includes support and a test for truncating stores, which are now possible thanks to the fpround pattern. llvm-svn: 329876
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